forked from M-Labs/artiq-zynq
use IOSERDES TTL
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@ -113,16 +113,16 @@ class NIST_CLOCK(ZC706):
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rtio_channels = []
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for i in range(16):
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if i % 4 == 3:
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phy = ttl_simple.InOut(platform.request("ttl", i))
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phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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else:
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phy = ttl_simple.Output(platform.request("ttl", i))
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phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for i in range(2):
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phy = ttl_simple.InOut(platform.request("pmt", i))
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phy = ttl_serdes_7series.InOut_8X(platform.request("pmt", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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@ -163,8 +163,7 @@ class NIST_QC2(ZC706):
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# All TTL channels are In+Out capable
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for i in range(40):
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phy = ttl_simple.InOut(
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platform.request("ttl", i))
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phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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