forked from M-Labs/artiq-zynq
gateware: make LEDs common to all variants
Makes quick testing easier.
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@ -109,8 +109,7 @@ class Simple(ZC706):
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rtio_channels = []
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for i in range(4):
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pad = platform.request("user_led", i)
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phy = ttl_simple.Output(pad)
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_rtio(rtio_channels)
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@ -127,6 +126,12 @@ class NIST_CLOCK(ZC706):
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platform.add_extension(nist_clock.fmc_adapter_io)
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for i in range(16):
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if i % 4 == 3:
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phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
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@ -142,10 +147,6 @@ class NIST_CLOCK(ZC706):
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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phy = ttl_simple.Output(platform.request("user_led", 1))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = ttl_simple.ClockGen(platform.request("la32_p"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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@ -175,7 +176,11 @@ class NIST_QC2(ZC706):
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platform.add_extension(nist_qc2.fmc_adapter_io)
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rtio_channels = []
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clock_generators = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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# All TTL channels are In+Out capable
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for i in range(40):
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@ -188,14 +193,7 @@ class NIST_QC2(ZC706):
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phy = ttl_simple.ClockGen(
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platform.request("clkout", i))
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self.submodules += phy
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clock_generators.append(rtio.Channel.from_phy(phy))
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phy = ttl_simple.Output(platform.request("user_led", 1))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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# add clock generators after TTLs
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rtio_channels += clock_generators
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for i in range(4):
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phy = spi2.SPIMaster(self.platform.request("spi", i))
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