forked from M-Labs/artiq-zynq
mark RTIO clock as asychronous to system clock
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7ee67db8e3
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68045ce0c5
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@ -71,6 +71,10 @@ class ZC706(SoCCore):
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self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk)
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self.csr_devices.append("rtio_crg")
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self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
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self.platform.add_false_path_constraints(
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self.ps7.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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