From 656cbf454648f034220a017aab67386d2631e4c7 Mon Sep 17 00:00:00 2001 From: sven-oxionics Date: Wed, 4 Oct 2023 16:49:09 +0100 Subject: [PATCH] kasli_soc: use sed_lanes value from HW description https://github.com/m-labs/artiq/pull/1745 added a field for setting the number of SED lanes to the HW description. This commit makes it so that the setting is used for Kasli Soc as well. --- src/gateware/kasli_soc.py | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 9b0e680..381f4f3 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -157,7 +157,9 @@ class GenericStandalone(SoCCore): self.rtio_channels.append(rtio.LogChannel()) self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) - self.submodules.rtio_core = rtio.Core(self.rtio_tsc, self.rtio_channels) + self.submodules.rtio_core = rtio.Core( + self.rtio_tsc, self.rtio_channels, lane_count=description["sed_lanes"] + ) self.csr_devices.append("rtio_core") if self.acpki: @@ -291,7 +293,9 @@ class GenericMaster(SoCCore): self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group) - self.submodules.rtio_core = rtio.Core(self.rtio_tsc, self.rtio_channels) + self.submodules.rtio_core = rtio.Core( + self.rtio_tsc, self.rtio_channels, lane_count=description["sed_lanes"] + ) self.csr_devices.append("rtio_core") if self.acpki: @@ -460,7 +464,9 @@ class GenericSatellite(SoCCore): self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0) self.csr_devices.append("rtio_dma") - self.submodules.local_io = SyncRTIO(self.rtio_tsc, self.rtio_channels) + self.submodules.local_io = SyncRTIO( + self.rtio_tsc, self.rtio_channels, lane_count=description["sed_lanes"] + ) self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors) self.submodules.cri_con = rtio.CRIInterconnectShared(