forked from M-Labs/artiq-zynq
satellites: add rtio_crg cfg
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78bc162749
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3cf86a6335
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@ -340,6 +340,7 @@ class GenericSatellite(SoCCore):
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
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self.csr_devices.append("rtio_crg")
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self.rustc_cfg["has_rtio_crg"] = None
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data_pads = [platform.request("sfp", i) for i in range(4)]
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@ -431,6 +431,7 @@ class _SatelliteBase(SoCCore):
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self.submodules.rtio_crg = RTIOClockMultiplier(self.sys_clk_freq)
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self.csr_devices.append("rtio_crg")
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self.rustc_cfg["has_rtio_crg"] = None
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fix_serdes_timing_path(self.platform)
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def add_rtio(self, rtio_channels):
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@ -392,7 +392,7 @@ fn drtiosat_process_errors() {
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#[cfg(has_rtio_crg)]
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fn init_rtio_crg(timer: GlobalTimer) {
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fn init_rtio_crg(timer: &mut GlobalTimer) {
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unsafe {
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csr::rtio_crg::pll_reset_write(0);
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}
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@ -401,10 +401,13 @@ fn init_rtio_crg(timer: GlobalTimer) {
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if !locked {
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error!("RTIO clock failed");
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}
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else {
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info!("RTIO PLL locked");
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}
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}
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#[cfg(not(has_rtio_crg))]
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fn init_rtio_crg(_timer: GlobalTimer) { }
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fn init_rtio_crg(_timer: &mut GlobalTimer) { }
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fn hardware_tick(ts: &mut u64, timer: &mut GlobalTimer) {
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let now = timer.get_time();
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@ -477,7 +480,7 @@ pub extern fn main_core0() -> i32 {
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unsafe {
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csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
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}
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init_rtio_crg(timer);
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init_rtio_crg(&mut timer);
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#[cfg(has_drtio_routing)]
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let mut repeaters = [repeater::Repeater::default(); csr::DRTIOREP.len()];
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