Support for DRTIO 100MHz (#155)

Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>

default.nix

@@ -8,7 +8,10 @@ let
   vivado = import <artiq-fast/vivado.nix> { inherit pkgs; };
   # FSBL configuration supplied by Vivado 2020.1 for these boards:
   fsblTargets = ["zc702" "zc706" "zed"];
-  sat_variants = ["satellite" "nist_clock_satellite" "nist_qc2_satellite" "acpki_nist_clock_satellite" "acpki_nist_qc2_satellite"];
+  sat_variants = [
+    "nist_clock_satellite" "nist_qc2_satellite" "acpki_nist_clock_satellite" "acpki_nist_qc2_satellite" 
+    "nist_clock_satellite_100mhz" "nist_qc2_satellite_100mhz" "acpki_nist_clock_satellite_100mhz" "acpki_nist_qc2_satellite_100mhz"
+  ];
   build = { target, variant, json ? null }: let
     szl = (import zynq-rs)."${target}-szl";
     fsbl = import "${zynq-rs}/nix/fsbl.nix" {
@@ -136,15 +139,19 @@ in
     (build { target = "zc706"; variant = "nist_clock"; }) //
     (build { target = "zc706"; variant = "nist_clock_master"; }) //
     (build { target = "zc706"; variant = "nist_clock_satellite"; }) //
+    (build { target = "zc706"; variant = "nist_clock_satellite_100mhz"; }) //
     (build { target = "zc706"; variant = "nist_qc2"; }) //
     (build { target = "zc706"; variant = "nist_qc2_master"; }) //
     (build { target = "zc706"; variant = "nist_qc2_satellite"; }) //
+    (build { target = "zc706"; variant = "nist_qc2_satellite_100mhz"; }) //
     (build { target = "zc706"; variant = "acpki_nist_clock"; }) //
     (build { target = "zc706"; variant = "acpki_nist_clock_master"; }) //
     (build { target = "zc706"; variant = "acpki_nist_clock_satellite"; }) //
+    (build { target = "zc706"; variant = "acpki_nist_clock_satellite_100mhz"; }) //
     (build { target = "zc706"; variant = "acpki_nist_qc2"; }) //
     (build { target = "zc706"; variant = "acpki_nist_qc2_master"; }) //
     (build { target = "zc706"; variant = "acpki_nist_qc2_satellite"; }) //
+    (build { target = "zc706"; variant = "acpki_nist_qc2_satellite_100mhz"; }) //
     (build { target = "kasli_soc"; variant = "demo"; json = ./demo.json; }) //
     (build { target = "kasli_soc"; variant = "master"; json = ./kasli-soc-master.json; }) //
     (build { target = "kasli_soc"; variant = "satellite"; json = ./kasli-soc-satellite.json; }) //

src/gateware/kasli_soc.py

@@ -180,7 +180,7 @@ class GenericStandalone(SoCCore):
 class GenericMaster(SoCCore):
     def __init__(self, description, acpki=False):
         sys_clk_freq = 125e6
-        rtio_clk_freq = 125e6
+        rtio_clk_freq = description["rtio_frequency"]
 
         self.acpki = acpki
         self.rustc_cfg = dict()
@@ -300,7 +300,7 @@ class GenericMaster(SoCCore):
 class GenericSatellite(SoCCore):
     def __init__(self, description, acpki=False):
         sys_clk_freq = 125e6  
-        rtio_clk_freq = 125e6
+        rtio_clk_freq = description["rtio_frequency"]
 
         self.acpki = acpki
         self.rustc_cfg = dict()

src/gateware/zc706.py

@@ -181,7 +181,7 @@ class ZC706(SoCCore):
 
 
 class _MasterBase(SoCCore):
-    def __init__(self, acpki=False):
+    def __init__(self, acpki=False, drtio100mhz=False):
         self.acpki = acpki
         self.rustc_cfg = dict()
 
@@ -195,6 +195,7 @@ class _MasterBase(SoCCore):
         platform.add_extension(si5324_fmc33)
 
         self.sys_clk_freq = 125e6
+        rtio_clk_freq = 100e6 if drtio100mhz else self.sys_clk_freq
 
         platform = self.platform
 
@@ -208,7 +209,8 @@ class _MasterBase(SoCCore):
         self.submodules.drtio_transceiver = gtx_7series.GTX(
             clock_pads=platform.request("si5324_clkout"),
             pads=data_pads,
-            sys_clk_freq=self.sys_clk_freq)
+            sys_clk_freq=self.sys_clk_freq,
+            rtio_clk_freq=rtio_clk_freq)
         self.csr_devices.append("drtio_transceiver")
 
         self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
@@ -247,7 +249,7 @@ class _MasterBase(SoCCore):
         self.add_csr_group("drtioaux", drtioaux_csr_group)
         self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
 
-        self.rustc_cfg["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
+        self.rustc_cfg["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
 
         self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
         self.csr_devices.append("si5324_rst_n")
@@ -313,7 +315,7 @@ class _MasterBase(SoCCore):
 
 
 class _SatelliteBase(SoCCore):
-    def __init__(self, acpki=False):
+    def __init__(self, acpki=False, drtio100mhz=False):
         self.acpki = acpki
         self.rustc_cfg = dict()
 
@@ -327,6 +329,7 @@ class _SatelliteBase(SoCCore):
         platform.add_extension(si5324_fmc33)
 
         self.sys_clk_freq = 125e6
+        rtio_clk_freq = 100e6 if drtio100mhz else self.sys_clk_freq
         platform = self.platform
 
         # SFP
@@ -342,7 +345,8 @@ class _SatelliteBase(SoCCore):
         self.submodules.drtio_transceiver = gtx_7series.GTX(
             clock_pads=platform.request("si5324_clkout"),
             pads=data_pads,
-            sys_clk_freq=self.sys_clk_freq)
+            sys_clk_freq=self.sys_clk_freq,
+            rtio_clk_freq=rtio_clk_freq)
         self.csr_devices.append("drtio_transceiver")
 
         drtioaux_csr_group = []
@@ -595,37 +599,35 @@ class _NIST_QC2_RTIO:
 
 
 class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO):
-    def __init__(self, acpki):
+    def __init__(self, acpki, drtio100mhz):
         ZC706.__init__(self, acpki)
         _NIST_CLOCK_RTIO.__init__(self)
 
 class NIST_CLOCK_Master(_MasterBase, _NIST_CLOCK_RTIO):
-    def __init__(self, acpki):
+    def __init__(self, acpki, drtio100mhz):
-        _MasterBase.__init__(self, acpki)
+        _MasterBase.__init__(self, acpki, drtio100mhz)
-
         _NIST_CLOCK_RTIO.__init__(self)
 
 class NIST_CLOCK_Satellite(_SatelliteBase, _NIST_CLOCK_RTIO):
-    def __init__(self, acpki):
+    def __init__(self, acpki, drtio100mhz):
-        _SatelliteBase.__init__(self, acpki)
+        _SatelliteBase.__init__(self, acpki, drtio100mhz)
         _NIST_CLOCK_RTIO.__init__(self)
 
 class NIST_QC2(ZC706, _NIST_QC2_RTIO):
-    def __init__(self, acpki):
+    def __init__(self, acpki, drtio100mhz):
         ZC706.__init__(self, acpki)
         _NIST_QC2_RTIO.__init__(self)
 
 class NIST_QC2_Master(_MasterBase, _NIST_QC2_RTIO):
-    def __init__(self, acpki):
+    def __init__(self, acpki, drtio100mhz):
-        _MasterBase.__init__(self, acpki)
+        _MasterBase.__init__(self, acpki, drtio100mhz)
         _NIST_QC2_RTIO.__init__(self)
 
 class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
-    def __init__(self, acpki):
+    def __init__(self, acpki, drtio100mhz):
-        _SatelliteBase.__init__(self, acpki)
+        _SatelliteBase.__init__(self, acpki, drtio100mhz)
         _NIST_QC2_RTIO.__init__(self)
 
-
 VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
                                                   NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]}
 
@@ -663,7 +665,7 @@ def main():
         help="build gateware into the specified directory")
     parser.add_argument("-V", "--variant", default="nist_clock",
                         help="variant: "
-                             "[acpki_]nist_clock/nist_qc2[_master/_satellite] "
+                             "[acpki_]nist_clock/nist_qc2[_master/_satellite][_100mhz]"
                              "(default: %(default)s)")
     args = parser.parse_args()
 
@@ -671,12 +673,15 @@ def main():
     acpki = variant.startswith("acpki_")
     if acpki:
         variant = variant[6:]
+    drtio100mhz = variant.endswith("_100mhz")
+    if drtio100mhz:
+        variant = variant[:-7]
     try:
         cls = VARIANTS[variant]
     except KeyError:
         raise SystemExit("Invalid variant (-V/--variant)")
 
-    soc = cls(acpki=acpki)
+    soc = cls(acpki=acpki, drtio100mhz=drtio100mhz)
     soc.finalize()
 
     if args.r is not None:

src/runtime/src/rtio_clocking.rs

@@ -23,6 +23,7 @@ pub enum RtioClock {
     Ext0_Synth0_125to125,
 }
 
+#[allow(unreachable_code)]
 fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock {
     let mut res = RtioClock::Default;
     if let Ok(clk) = cfg.read_str("rtio_clock") {
@@ -46,9 +47,22 @@ fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock {
         warn!("error reading configuration. Falling back to default.");
     }
     if res == RtioClock::Default {
+        #[cfg(rtio_frequency="100.0")]
+        {
+            warn!("Using default configuration - internal 100MHz RTIO clock.");
+            return RtioClock::Int_100;
+        }
+        #[cfg(rtio_frequency="125.0")]
+        {
             warn!("Using default configuration - internal 125MHz RTIO clock.");
             return RtioClock::Int_125;
         }
+        // anything else
+        {
+            warn!("Using default configuration - internal 125MHz RTIO clock.");
+            return RtioClock::Int_125;
+        }
+    }
     res
 }
 

src/satman/src/main.rs

@@ -398,7 +398,7 @@ fn hardware_tick(ts: &mut u64, timer: &mut GlobalTimer) {
     }
 }
 
-#[cfg(has_si5324)]
+#[cfg(all(has_si5324, rtio_frequency = "125.0"))]
 const SI5324_SETTINGS: si5324::FrequencySettings
     = si5324::FrequencySettings {
     n1_hs  : 5,
@@ -411,6 +411,19 @@ const SI5324_SETTINGS: si5324::FrequencySettings
     crystal_ref: true
 };
 
+#[cfg(all(has_si5324, rtio_frequency = "100.0"))]
+const SI5324_SETTINGS: si5324::FrequencySettings
+    = si5324::FrequencySettings {
+    n1_hs  : 5,
+    nc1_ls : 10,
+    n2_hs  : 10,
+    n2_ls  : 250,
+    n31    : 50,
+    n32    : 50,
+    bwsel  : 4,
+    crystal_ref: true
+};
+
 static mut LOG_BUFFER: [u8; 1<<17] = [0; 1<<17];
 
 #[no_mangle]