forked from M-Labs/artiq-zynq
Undo most of Si5324 unification (5c054cc901
)
This reverts most of 5c054cc901
, as it turns out that
si5324::setup is in fact also used to configure the
chip for operation as a DRTIO satellite.
This commit is contained in:
parent
5c054cc901
commit
2ddb4d259f
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@ -219,11 +219,8 @@ pub fn bypass(i2c: &mut I2c, input: Input, timer: &mut GlobalTimer) -> Result<()
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Ok(())
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}
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pub fn setup(i2c: &mut I2c, settings: &FrequencySettings, ext_input: Input, timer: &mut GlobalTimer) -> Result<()> {
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pub fn setup(i2c: &mut I2c, settings: &FrequencySettings, input: Input, timer: &mut GlobalTimer) -> Result<()> {
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let s = map_frequency_settings(settings)?;
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// FREE_RUN=1 routes XA/XB to CKIN2.
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let input = if settings.crystal_ref { Input::Ckin2 } else { ext_input };
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let cksel_reg = match input {
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Input::Ckin1 => 0b00,
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Input::Ckin2 => 0b01,
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@ -121,9 +121,10 @@ const SI5324_EXT_INPUT: si5324::Input = si5324::Input::Ckin1;
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#[cfg(has_si5324)]
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fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
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let si5324_settings = match clk {
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let (si5324_settings, si5324_ref_input) = match clk {
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RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW
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info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
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(
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si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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@ -133,10 +134,13 @@ fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
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n32 : 6,
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bwsel : 4,
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crystal_ref: false
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}
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},
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SI5324_EXT_INPUT
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)
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},
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RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth
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info!("using 100MHz reference to make 125MHz RTIO clock with PLL");
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(
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si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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@ -146,10 +150,13 @@ fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
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n32 : 52,
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bwsel : 4,
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crystal_ref: false
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}
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},
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SI5324_EXT_INPUT
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)
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},
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RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth
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info!("using 125MHz reference to make 125MHz RTIO clock with PLL");
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(
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si5324::FrequencySettings {
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n1_hs : 5,
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nc1_ls : 8,
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@ -159,10 +166,13 @@ fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
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n32 : 63,
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bwsel : 4,
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crystal_ref: false
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}
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},
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SI5324_EXT_INPUT
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)
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},
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RtioClock::Int_150 => { // 150MHz output, from crystal
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info!("using internal 150MHz RTIO clock");
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(
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si5324::FrequencySettings {
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n1_hs : 9,
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nc1_ls : 4,
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@ -172,10 +182,13 @@ fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
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n32 : 7139,
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bwsel : 3,
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crystal_ref: true
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}
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},
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si5324::Input::Ckin2
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)
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},
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RtioClock::Int_100 => { // 100MHz output, from crystal
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info!("using internal 100MHz RTIO clock");
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(
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si5324::FrequencySettings {
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n1_hs : 9,
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nc1_ls : 6,
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@ -185,10 +198,13 @@ fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
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n32 : 7139,
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bwsel : 3,
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crystal_ref: true
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}
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},
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si5324::Input::Ckin2
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)
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},
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RtioClock::Int_125 => { // 125MHz output, from crystal, 7 Hz
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info!("using internal 125MHz RTIO clock");
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(
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si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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@ -198,10 +214,13 @@ fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
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n32 : 4565,
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bwsel : 4,
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crystal_ref: true
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}
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}
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_ => { // 125MHz output like above, default (if chosen option is not supported)
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warn!("rtio_clock setting '{:?}' is not supported. Falling back to default internal 125MHz RTIO clock.", clk);
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},
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si5324::Input::Ckin2
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)
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},
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_ => { // same setting as Int_125, but fallback to default
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warn!("rtio_clock setting '{:?}' is unsupported. Falling back to default internal 125MHz RTIO clock.", clk);
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(
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si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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@ -211,10 +230,12 @@ fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
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n32 : 4565,
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bwsel : 4,
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crystal_ref: true
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}
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},
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si5324::Input::Ckin2
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)
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}
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};
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si5324::setup(i2c, &si5324_settings, SI5324_EXT_INPUT, timer).expect("cannot initialize Si5324");
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si5324::setup(i2c, &si5324_settings, si5324_ref_input, timer).expect("cannot initialize Si5324");
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}
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pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
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