forked from M-Labs/artiq-zynq
satellite: port analyzer, drtio packets
This commit is contained in:
parent
c5aac198f2
commit
259b0ba1b7
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@ -1,8 +1,8 @@
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use core_io::{Error as IoError, Read, Write};
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use core_io::{Error as IoError, Read, Write};
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use io::proto::{ProtoRead, ProtoWrite};
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use io::proto::{ProtoRead, ProtoWrite};
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/* 512 (max size) - 4 (CRC) - 1 (packet ID) - 1 (destination) - 4 (trace ID) - 1 (last) - 2 (length) */
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pub const DMA_TRACE_MAX_SIZE: usize = /*max size*/512 - /*CRC*/4 - /*packet ID*/1 - /*trace ID*/4 - /*last*/1 -/*length*/2;
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pub const DMA_TRACE_MAX_SIZE: usize = 499;
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pub const ANALYZER_MAX_SIZE: usize = /*max size*/512 - /*CRC*/4 - /*packet ID*/1 - /*last*/1 - /*length*/2;
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#[derive(Debug)]
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#[derive(Debug)]
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pub enum Error {
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pub enum Error {
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@ -136,6 +136,23 @@ pub enum Packet {
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succeeded: bool,
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succeeded: bool,
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},
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},
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AnalyzerHeaderRequest {
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destination: u8
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},
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AnalyzerHeader {
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sent_bytes: u32,
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total_byte_count: u64,
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overflow_occurred: bool,
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},
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AnalyzerDataRequest {
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destination: u8,
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},
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AnalyzerData {
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last: bool,
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length: u16,
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data: [u8; ANALYZER_MAX_SIZE],
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},
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DmaAddTraceRequest {
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DmaAddTraceRequest {
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destination: u8,
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destination: u8,
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id: u32,
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id: u32,
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@ -298,6 +315,29 @@ impl Packet {
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succeeded: reader.read_bool()?,
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succeeded: reader.read_bool()?,
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},
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},
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0xa0 => Packet::AnalyzerHeaderRequest {
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destination: reader.read_u8()?
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},
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0xa1 => Packet::AnalyzerHeader {
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sent_bytes: reader.read_u32()?,
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total_byte_count: reader.read_u64()?,
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overflow_occurred: reader.read_bool()?,
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},
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0xa2 => Packet::AnalyzerDataRequest {
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destination: reader.read_u8()?
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},
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0xa3 => {
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let last = reader.read_bool()?;
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let length = reader.read_u16()?;
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let mut data: [u8; ANALYZER_MAX_SIZE] = [0; ANALYZER_MAX_SIZE];
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reader.read_exact(&mut data[0..length as usize])?;
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Packet::AnalyzerData {
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last: last,
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length: length,
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data: data
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}
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},
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0xb0 => {
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0xb0 => {
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let destination = reader.read_u8()?;
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let destination = reader.read_u8()?;
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let id = reader.read_u32()?;
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let id = reader.read_u32()?;
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@ -526,6 +566,35 @@ impl Packet {
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writer.write_bool(succeeded)?;
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writer.write_bool(succeeded)?;
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}
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}
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Packet::AnalyzerHeaderRequest { destination } => {
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writer.write_u8(0xa0)?;
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writer.write_u8(destination)?;
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}
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Packet::AnalyzerHeader {
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sent_bytes,
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total_byte_count,
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overflow_occurred
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} => {
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writer.write_u8(0xa1)?;
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writer.write_u32(sent_bytes)?;
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writer.write_u64(total_byte_count)?;
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writer.write_bool(overflow_occurred)?;
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}
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Packet::AnalyzerDataRequest { destination } => {
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writer.write_u8(0xa2)?;
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writer.write_u8(destination)?;
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}
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Packet::AnalyzerData {
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last,
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length,
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data
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} => {
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writer.write_u8(0xa3)?;
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writer.write_bool(last)?;
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writer.write_u16(length)?;
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writer.write_all(&data[0..length as usize])?;
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}
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Packet::DmaAddTraceRequest {
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Packet::DmaAddTraceRequest {
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destination,
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destination,
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id,
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id,
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@ -0,0 +1,106 @@
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use libboard_artiq::pl::csr;
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use libcortex_a9::cache;
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use libboard_artiq::drtioaux_proto::ANALYZER_MAX_SIZE;
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const BUFFER_SIZE: usize = 512 * 1024;
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#[repr(align(64))]
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struct Buffer {
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data: [u8; BUFFER_SIZE],
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}
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static mut BUFFER: Buffer = Buffer {
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data: [0; BUFFER_SIZE]
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};
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fn arm() {
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unsafe {
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let base_addr = &mut BUFFER.data[0] as *mut _ as usize;
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let last_addr = &mut BUFFER.data[BUFFER_SIZE - 1] as *mut _ as usize;
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csr::rtio_analyzer::dma_base_address_write(base_addr as u32);
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csr::rtio_analyzer::message_encoder_overflow_reset_write(1);
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csr::rtio_analyzer::dma_last_address_write(last_addr as u32);
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csr::rtio_analyzer::dma_reset_write(1);
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csr::rtio_analyzer::enable_write(1);
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}
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}
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fn disarm() {
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unsafe {
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csr::rtio_analyzer::enable_write(0);
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while csr::rtio_analyzer::busy_read() != 0 {}
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cache::dcci_slice(&BUFFER.data);
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}
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}
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pub struct Analyzer {
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// necessary for keeping track of sent data
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sent_bytes: usize,
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data_iter: usize
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}
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pub struct Header {
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pub total_byte_count: u64,
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pub sent_bytes: u32,
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pub error: bool
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}
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pub struct AnalyzerSliceMeta {
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pub len: u16,
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pub last: bool
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}
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impl Analyzer {
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pub fn new() -> Analyzer {
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// create and arm new Analyzer
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arm();
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Analyzer {
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sent_bytes: 0,
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data_iter: 0
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}
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}
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fn drop(&mut self) {
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disarm();
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}
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pub fn get_header(&mut self) -> Header {
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disarm();
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let overflow = unsafe { csr::rtio_analyzer::message_encoder_overflow_read() != 0 };
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let bus_err = unsafe { csr::rtio_analyzer::dma_bus_error_read() != 0 };
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let total_byte_count = unsafe { csr::rtio_analyzer::dma_byte_count_read() as u64 };
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let wraparound = total_byte_count >= BUFFER_SIZE as u64;
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self.sent_bytes = if wraparound { BUFFER_SIZE } else { total_byte_count as usize };
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self.data_iter = if wraparound { (total_byte_count % BUFFER_SIZE as u64) as usize } else { 0 };
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Header {
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total_byte_count: total_byte_count,
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sent_bytes: self.sent_bytes as u32,
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error: overflow | bus_err
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}
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}
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pub fn get_data(&mut self, data_slice: &mut [u8; ANALYZER_MAX_SIZE]) -> AnalyzerSliceMeta {
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let data = unsafe { &BUFFER.data[..] };
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let i = self.data_iter;
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let len = if i + ANALYZER_MAX_SIZE < self.sent_bytes { ANALYZER_MAX_SIZE } else { self.sent_bytes - i };
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let last = i + len == self.sent_bytes;
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if i + len >= BUFFER_SIZE {
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data_slice[..len].clone_from_slice(&data[i..BUFFER_SIZE]);
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data_slice[..len].clone_from_slice(&data[..(i+len) % BUFFER_SIZE]);
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} else {
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data_slice[..len].clone_from_slice(&data[i..i+len]);
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}
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self.data_iter += len;
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if last {
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arm();
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}
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AnalyzerSliceMeta {
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len: len as u16,
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last: last
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}
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}
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}
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@ -20,6 +20,7 @@ extern crate alloc;
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use core::sync::atomic::{AtomicBool, Ordering};
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use core::sync::atomic::{AtomicBool, Ordering};
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use analyzer::Analyzer as Analyzer;
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use dma::Manager as DmaManager;
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use dma::Manager as DmaManager;
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use embedded_hal::blocking::delay::DelayUs;
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use embedded_hal::blocking::delay::DelayUs;
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#[cfg(feature = "target_kasli_soc")]
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#[cfg(feature = "target_kasli_soc")]
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@ -40,6 +41,7 @@ use libsupport_zynq::ram;
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mod dma;
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mod dma;
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mod repeater;
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mod repeater;
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mod analyzer;
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fn drtiosat_reset(reset: bool) {
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fn drtiosat_reset(reset: bool) {
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unsafe {
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unsafe {
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@ -95,6 +97,7 @@ fn process_aux_packet(
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timer: &mut GlobalTimer,
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timer: &mut GlobalTimer,
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i2c: &mut I2c,
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i2c: &mut I2c,
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dma_manager: &mut DmaManager,
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dma_manager: &mut DmaManager,
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analyzer: &mut Analyzer,
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) -> Result<(), drtioaux::Error> {
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) -> Result<(), drtioaux::Error> {
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// In the code below, *_chan_sel_write takes an u8 if there are fewer than 256 channels,
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// In the code below, *_chan_sel_write takes an u8 if there are fewer than 256 channels,
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// and u16 otherwise; hence the `as _` conversion.
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// and u16 otherwise; hence the `as _` conversion.
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)
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)
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}
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}
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drtioaux::Packet::AnalyzerHeaderRequest { destination: _destination } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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let header = analyzer.get_header();
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drtioaux::send(0, &drtioaux::Packet::AnalyzerHeader {
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total_byte_count: header.total_byte_count,
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sent_bytes: header.sent_bytes,
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overflow_occurred: header.overflow,
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})
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}
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drtioaux::Packet::AnalyzerDataRequest { destination: _destination } => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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let mut data_slice: [u8; ANALYZER_MAX_SIZE] = [0; ANALYZER_MAX_SIZE];
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let meta = analyzer.get_data(&mut data_slice);
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drtioaux::send(0, &drtioaux::Packet::AnalyzerData {
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last: meta.last,
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length: meta.len,
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data: data_slice,
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})
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}
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drtioaux::Packet::DmaAddTraceRequest {
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drtioaux::Packet::DmaAddTraceRequest {
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destination: _destination,
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destination: _destination,
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id,
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id,
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@ -455,10 +478,11 @@ fn process_aux_packets(
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timer: &mut GlobalTimer,
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timer: &mut GlobalTimer,
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i2c: &mut I2c,
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i2c: &mut I2c,
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dma_manager: &mut DmaManager,
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dma_manager: &mut DmaManager,
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analyzer: &mut Analyzer,
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) {
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) {
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let result = drtioaux::recv(0).and_then(|packet| {
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let result = drtioaux::recv(0).and_then(|packet| {
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if let Some(packet) = packet {
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if let Some(packet) = packet {
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process_aux_packet(repeaters, routing_table, rank, packet, timer, i2c, dma_manager)
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process_aux_packet(repeaters, routing_table, rank, packet, timer, i2c, dma_manager, analyzer)
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} else {
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} else {
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Ok(())
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Ok(())
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}
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}
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@ -635,6 +659,8 @@ pub extern "C" fn main_core0() -> i32 {
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// are cleared out for a clean slate on subsequent connections,
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// are cleared out for a clean slate on subsequent connections,
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// without a manual intervention.
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// without a manual intervention.
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let mut dma_manager = DmaManager::new();
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let mut dma_manager = DmaManager::new();
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// same for RTIO Analyzer
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let mut analyzer = Analyzer::new();
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drtioaux::reset(0);
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drtioaux::reset(0);
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drtiosat_reset(false);
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drtiosat_reset(false);
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@ -649,6 +675,7 @@ pub extern "C" fn main_core0() -> i32 {
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&mut timer,
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&mut timer,
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&mut i2c,
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&mut i2c,
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&mut dma_manager,
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&mut dma_manager,
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&mut analyzer,
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);
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);
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#[allow(unused_mut)]
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#[allow(unused_mut)]
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for mut rep in repeaters.iter_mut() {
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for mut rep in repeaters.iter_mut() {
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