forked from M-Labs/artiq-zynq
runtime: initialize more
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@ -24,6 +24,16 @@ version = "0.1.26"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "036b035e9ebcd705affece16319223d19f229e2358be6e3b7b094e57193312e6"
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[[package]]
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name = "libasync"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#526cfe7577c189687ed1fdca512120dd1460bb80"
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dependencies = [
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"libcortex_a9",
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"pin-utils",
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"smoltcp",
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]
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[[package]]
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name = "libboard_zynq"
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version = "0.0.0"
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@ -80,6 +90,12 @@ version = "0.7.1"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "fdcec5e97041c7f0f1c5b7d93f12e57293c831c646f4cc7a5db59460c7ea8de6"
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[[package]]
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name = "pin-utils"
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version = "0.1.0-alpha.4"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "5894c618ce612a3fa23881b152b608bafb8c56cfc22f434a3ba3120b40f7b587"
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[[package]]
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name = "r0"
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version = "1.0.0"
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@ -90,6 +106,7 @@ checksum = "bd7a31eed1591dcbc95d92ad7161908e72f4677f8fabf2a32ca49b4237cbf211"
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name = "runtime"
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version = "0.1.0"
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dependencies = [
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"libasync",
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"libboard_zynq",
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"libsupport_zynq",
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]
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@ -7,9 +7,9 @@ edition = "2018"
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[features]
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target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706"]
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target_cora_z7_10 = ["libboard_zynq/target_cora_z7_10", "libsupport_zynq/target_cora_z7_10"]
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default = ["target_zc706"]
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[dependencies]
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libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libsupport_zynq = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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libasync = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
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@ -3,9 +3,22 @@
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extern crate alloc;
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use libboard_zynq::println;
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use libsupport_zynq::ram;
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use core::{cmp, str};
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use core::mem::transmute;
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use libboard_zynq::{
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println,
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self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll},
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smoltcp::{
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wire::{EthernetAddress, IpAddress, IpCidr},
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iface::{NeighborCache, EthernetInterfaceBuilder, Routes},
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time::Instant,
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},
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};
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use libsupport_zynq::{
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ram, alloc::{vec, vec::Vec},
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};
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use libasync::smoltcp::Sockets;
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mod pl;
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@ -22,10 +35,63 @@ fn identifier_read(buf: &mut [u8]) -> &str {
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}
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}
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const HWADDR: [u8; 6] = [0, 0x23, 0xab, 0xad, 0x1d, 0xea];
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#[no_mangle]
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pub fn main_core0() {
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println!("[CORE0] hello world {}", identifier_read(&mut [0; 64]));
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loop {}
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println!("ARTIQ runtime starting...");
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const CPU_FREQ: u32 = 800_000_000;
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ArmPll::setup(2 * CPU_FREQ);
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Clocks::set_cpu_freq(CPU_FREQ);
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IoPll::setup(1_000_000_000);
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libboard_zynq::stdio::drop_uart(); // why?
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let mut ddr = zynq::ddr::DdrRam::new();
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ram::init_alloc(&mut ddr);
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println!("Detected gateware: {}", identifier_read(&mut [0; 64]));
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let eth = zynq::eth::Eth::default(HWADDR.clone());
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const RX_LEN: usize = 8;
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let mut rx_descs = (0..RX_LEN)
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.map(|_| zynq::eth::rx::DescEntry::zeroed())
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.collect::<Vec<_>>();
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let mut rx_buffers = vec![zynq::eth::Buffer::new(); RX_LEN];
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// Number of transmission buffers (minimum is two because with
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// one, duplicate packet transmission occurs)
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const TX_LEN: usize = 8;
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let mut tx_descs = (0..TX_LEN)
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.map(|_| zynq::eth::tx::DescEntry::zeroed())
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.collect::<Vec<_>>();
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let mut tx_buffers = vec![zynq::eth::Buffer::new(); TX_LEN];
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let eth = eth.start_rx(&mut rx_descs, &mut rx_buffers);
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let mut eth = eth.start_tx(
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// HACK
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unsafe { transmute(tx_descs.as_mut_slice()) },
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unsafe { transmute(tx_buffers.as_mut_slice()) },
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);
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let ethernet_addr = EthernetAddress(HWADDR);
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let local_addr = IpAddress::v4(192, 168, 1, 52);
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let mut ip_addrs = [IpCidr::new(local_addr, 24)];
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let mut routes_storage = vec![None; 4];
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let routes = Routes::new(&mut routes_storage[..]);
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let mut neighbor_storage = vec![None; 256];
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let neighbor_cache = NeighborCache::new(&mut neighbor_storage[..]);
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let mut iface = EthernetInterfaceBuilder::new(&mut eth)
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.ethernet_addr(ethernet_addr)
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.ip_addrs(&mut ip_addrs[..])
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.routes(routes)
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.neighbor_cache(neighbor_cache)
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.finalize();
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Sockets::init(32);
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let mut time = 0u32;
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Sockets::run(&mut iface, || {
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time += 1;
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Instant::from_millis(time)
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});
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}
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#[no_mangle]
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