forked from M-Labs/artiq-zynq
analyzer: report AXI bus errors
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9a8f8e2d7b
commit
21135c6a41
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@ -22,6 +22,7 @@ class AXIDMAWriter(Module, AutoCSR):
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self.base_address = CSRStorage(aw, alignment_bits=alignment_bits)
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self.base_address = CSRStorage(aw, alignment_bits=alignment_bits)
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self.last_address = CSRStorage(aw, alignment_bits=alignment_bits)
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self.last_address = CSRStorage(aw, alignment_bits=alignment_bits)
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self.byte_count = CSRStatus(32) # only read when shut down
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self.byte_count = CSRStatus(32) # only read when shut down
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self.bus_error = CSRStatus()
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self.make_request = Signal()
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self.make_request = Signal()
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self.sink = stream.Endpoint([("data", dw)])
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self.sink = stream.Endpoint([("data", dw)])
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@ -82,6 +83,11 @@ class AXIDMAWriter(Module, AutoCSR):
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]
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]
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self.comb += membus.b.ready.eq(1)
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self.comb += membus.b.ready.eq(1)
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self.sync += [
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If(self.reset.re, self.bus_error.status.eq(0)),
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If(membus.b.valid & membus.b.ready & (membus.b.resp != axi.Response.okay),
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self.bus_error.status.eq(1))
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]
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class Analyzer(Module, AutoCSR):
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class Analyzer(Module, AutoCSR):
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@ -44,7 +44,7 @@ fn disarm() {
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struct Header {
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struct Header {
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sent_bytes: u32,
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sent_bytes: u32,
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total_byte_count: u64,
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total_byte_count: u64,
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overflow_occurred: bool,
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error_occurred: bool,
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log_channel: u8,
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log_channel: u8,
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dds_onehot_sel: bool
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dds_onehot_sel: bool
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}
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}
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@ -52,7 +52,7 @@ struct Header {
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async fn write_header(stream: &mut TcpStream, header: &Header) -> Result<(), Error> {
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async fn write_header(stream: &mut TcpStream, header: &Header) -> Result<(), Error> {
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write_i32(stream, header.sent_bytes as i32).await?;
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write_i32(stream, header.sent_bytes as i32).await?;
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write_i64(stream, header.total_byte_count as i64).await?;
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write_i64(stream, header.total_byte_count as i64).await?;
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write_i8(stream, header.overflow_occurred as i8).await?;
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write_i8(stream, header.error_occurred as i8).await?;
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write_i8(stream, header.log_channel as i8).await?;
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write_i8(stream, header.log_channel as i8).await?;
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write_i8(stream, header.dds_onehot_sel as i8).await?;
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write_i8(stream, header.dds_onehot_sel as i8).await?;
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Ok(())
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Ok(())
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@ -63,14 +63,22 @@ async fn handle_connection(stream: &mut TcpStream) -> Result<(), Error> {
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let data = unsafe { &BUFFER.data[..] };
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let data = unsafe { &BUFFER.data[..] };
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let overflow_occurred = unsafe { pl::csr::rtio_analyzer::message_encoder_overflow_read() != 0 };
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let overflow_occurred = unsafe { pl::csr::rtio_analyzer::message_encoder_overflow_read() != 0 };
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let bus_error_occurred = unsafe { pl::csr::rtio_analyzer::dma_bus_error_read() != 0 };
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let total_byte_count = unsafe { pl::csr::rtio_analyzer::dma_byte_count_read() as u64 };
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let total_byte_count = unsafe { pl::csr::rtio_analyzer::dma_byte_count_read() as u64 };
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let pointer = (total_byte_count % BUFFER_SIZE as u64) as usize;
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let pointer = (total_byte_count % BUFFER_SIZE as u64) as usize;
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let wraparound = total_byte_count >= BUFFER_SIZE as u64;
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let wraparound = total_byte_count >= BUFFER_SIZE as u64;
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if overflow_occurred {
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warn!("overflow occured");
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}
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if bus_error_occurred {
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warn!("bus error occured");
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}
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let header = Header {
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let header = Header {
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total_byte_count: total_byte_count,
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total_byte_count: total_byte_count,
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sent_bytes: if wraparound { BUFFER_SIZE as u32 } else { total_byte_count as u32 },
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sent_bytes: if wraparound { BUFFER_SIZE as u32 } else { total_byte_count as u32 },
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overflow_occurred: overflow_occurred,
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error_occurred: overflow_occurred | bus_error_occurred,
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log_channel: pl::csr::CONFIG_RTIO_LOG_CHANNEL as u8,
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log_channel: pl::csr::CONFIG_RTIO_LOG_CHANNEL as u8,
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dds_onehot_sel: true // kept for backward compatibility of analyzer dumps
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dds_onehot_sel: true // kept for backward compatibility of analyzer dumps
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};
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};
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