forked from M-Labs/artiq-zynq
qc2: add 4 edge counters to the end of rtio
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c484153348
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0c1036cb0c
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@ -78,6 +78,14 @@ device_db["ad9914dds1"] = {
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"arguments": {"sysclk": 3e9, "bus_channel": 50, "channel": 1},
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"arguments": {"sysclk": 3e9, "bus_channel": 50, "channel": 1},
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}
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}
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for i in range(4):
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device_db["ttl"+str(i)+"_counter"] = {
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"type": "local",
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"module": "artiq.coredevice.edge_counter",
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"class": "EdgeCounter",
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"arguments": {"channel": 52+i}
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}
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# for ARTIQ test suite
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# for ARTIQ test suite
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device_db.update(
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device_db.update(
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loop_out="ttl0",
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loop_out="ttl0",
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@ -13,7 +13,7 @@ from misoc.interconnect.csr import *
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from misoc.integration import cpu_interface
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from misoc.integration import cpu_interface
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from artiq.gateware import rtio, nist_clock, nist_qc2
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from artiq.gateware import rtio, nist_clock, nist_qc2
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2, edge_counter
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import dma
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import dma
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import analyzer
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import analyzer
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@ -215,6 +215,7 @@ class NIST_QC2(ZC706):
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platform.add_extension(leds_fmc33)
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platform.add_extension(leds_fmc33)
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rtio_channels = []
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rtio_channels = []
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edge_counter_phy = []
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for i in range(4):
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led_33", i))
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phy = ttl_simple.Output(platform.request("user_led_33", i))
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@ -226,6 +227,9 @@ class NIST_QC2(ZC706):
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phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
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phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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# first four TTLs will also have edge counters
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if i < 4:
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edge_counter_phy.append(phy)
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# CLK0, CLK1 are for clock generators, on backplane SMP connectors
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# CLK0, CLK1 are for clock generators, on backplane SMP connectors
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for i in range(2):
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for i in range(2):
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@ -246,6 +250,11 @@ class NIST_QC2(ZC706):
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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for phy in edge_counter_phy:
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counter = edge_counter.SimpleEdgeCounter(phy.input_state)
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self.submodules += counter
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rtio_channels.append(rtio.Channel.from_phy(counter))
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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rtio_channels.append(rtio.LogChannel())
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