forked from M-Labs/humpback-dds
395 lines
11 KiB
Rust
395 lines
11 KiB
Rust
#![no_main]
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#![no_std]
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use core::sync::atomic::{AtomicU32, Ordering};
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#[macro_use]
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extern crate log;
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use cortex_m;
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use cortex_m_rt::{
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entry,
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exception,
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};
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extern crate smoltcp;
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use stm32h7xx_hal::ethernet;
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use stm32h7xx_hal::hal::digital::v2::InputPin;
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use stm32h7xx_hal::rcc::CoreClocks;
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use stm32h7xx_hal::{pac, prelude::*, spi, stm32, stm32::interrupt};
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use core::{
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str,
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fmt::Write
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};
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use core::mem::uninitialized;
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// Exception: no phy::wait
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//use smoltcp::phy::wait as phy_wait;
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use smoltcp::wire::{IpAddress, IpCidr};
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use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder};
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use smoltcp::socket::SocketSet;
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use smoltcp::socket::{SocketHandle, TcpSocket, TcpSocketBuffer};
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use smoltcp::time::{Duration, Instant};
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// use smoltcp::log;
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// Use embedded-nal to access smoltcp
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use embedded_nal::TcpStack;
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use firmware;
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use firmware::{
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cpld::{
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CPLD,
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},
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scpi::{
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HelloWorldCommand,
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Channel0SwitchCommand,
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Channel1SwitchCommand,
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Channel2SwitchCommand,
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Channel3SwitchCommand,
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Channel0AttenuationCommand,
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Channel1AttenuationCommand,
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Channel2AttenuationCommand,
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Channel3AttenuationCommand,
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ClockSourceCommand,
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ClockDivisionCommand,
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ProfileCommand
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},
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Urukul, scpi_root, recursive_scpi_tree, scpi_tree
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};
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use scpi::prelude::*;
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use scpi::ieee488::commands::*;
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use scpi::scpi::commands::*;
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use scpi::{
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ieee488_cls,
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ieee488_ese,
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ieee488_esr,
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ieee488_idn,
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ieee488_opc,
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ieee488_rst,
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ieee488_sre,
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ieee488_stb,
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ieee488_tst,
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ieee488_wai,
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scpi_crate_version,
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scpi_status,
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scpi_system,
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};
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#[path = "util/logger.rs"]
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mod logger;
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/// Configure SYSTICK for 1ms timebase
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fn systick_init(syst: &mut stm32::SYST, clocks: CoreClocks) {
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let c_ck_mhz = clocks.c_ck().0 / 1_000_000;
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let syst_calib = 0x3E8;
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syst.set_clock_source(cortex_m::peripheral::syst::SystClkSource::Core);
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syst.set_reload((syst_calib * c_ck_mhz) - 1);
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syst.enable_interrupt();
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syst.enable_counter();
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}
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/// ======================================================================
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/// Entry point
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/// ======================================================================
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/// TIME is an atomic u32 that counts milliseconds. Although not used
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/// here, it is very useful to have for network protocols
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static TIME: AtomicU32 = AtomicU32::new(0);
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/// Locally administered MAC address
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const MAC_ADDRESS: [u8; 6] = [0x02, 0x00, 0x11, 0x22, 0x33, 0x44];
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/// Ethernet descriptor rings are a global singleton
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#[link_section = ".sram3.eth"]
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static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new();
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// Theoratical maximum number of socket that can be handled
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const SOCKET_COUNT: usize = 2;
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// Give buffer sizes of transmitting and receiving TCP packets
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const BUFFER_SIZE: usize = 2048;
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// the program entry point
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#[entry]
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fn main() -> ! {
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// logger::semihosting_init();
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let mut cp = cortex_m::Peripherals::take().unwrap();
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let dp = pac::Peripherals::take().unwrap();
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// Initialise power...
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let pwr = dp.PWR.constrain();
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let vos = pwr.freeze();
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// Initialise SRAM3
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dp.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit());
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// Initialise clocks...
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let rcc = dp.RCC.constrain();
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let ccdr = rcc
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.use_hse(8.mhz())
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.sys_ck(200.mhz())
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.hclk(200.mhz())
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.pll1_r_ck(400.mhz()) // for TRACECK
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.pll1_q_ck(48.mhz()) // for SPI
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.freeze(vos, &dp.SYSCFG);
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unsafe {
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logger::enable_itm(&dp.DBGMCU, &mut cp.DCB, &mut cp.ITM);
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}
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// Get the delay provider.
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let delay = cp.SYST.delay(ccdr.clocks);
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// Initialise system...
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cp.SCB.invalidate_icache();
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cp.SCB.enable_icache();
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cp.DWT.enable_cycle_counter();
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// Initialise IO...
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let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
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let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
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let gpioc = dp.GPIOC.split(ccdr.peripheral.GPIOC);
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let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD);
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let gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE);
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let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);
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let gpiog = dp.GPIOG.split(ccdr.peripheral.GPIOG);
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// gpiob.pb3.into_alternate_af0().set_speed(Speed::VeryHigh);
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logger::init();
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// Setup CDONE for checking
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let fpga_cdone = gpiod.pd15.into_pull_up_input();
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match fpga_cdone.is_high() {
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Ok(true) => debug!("FPGA is ready."),
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Ok(_) => debug!("FPGA is in reset state."),
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Err(_) => debug!("Error: Cannot read C_DONE"),
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};
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// Setup Urukul
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/*
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* Using SPI1, AF5
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* SCLK -> PA5
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* MOSI -> PB5
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* MISO -> PA6
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* CS -> 0: PB12, 1: PA15, 2: PC7
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*/
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let sclk = gpioa.pa5.into_alternate_af5();
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let mosi = gpiob.pb5.into_alternate_af5();
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let miso = gpioa.pa6.into_alternate_af5();
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let (cs0, cs1, cs2) = (
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gpiob.pb12.into_push_pull_output(),
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gpioa.pa15.into_push_pull_output(),
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gpioc.pc7.into_push_pull_output(),
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);
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/*
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* I/O_Update -> PB15
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*/
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let io_update = gpiob.pb15.into_push_pull_output();
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let spi = dp.SPI1.spi(
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(sclk, miso, mosi),
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spi::MODE_0,
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3.mhz(),
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ccdr.peripheral.SPI1,
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&ccdr.clocks,
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);
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let switch = CPLD::new(spi, (cs0, cs1, cs2), io_update);
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let parts = switch.split();
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let mut urukul = Urukul::new(
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parts.spi1, parts.spi2, parts.spi3, parts.spi4, parts.spi5, parts.spi6, parts.spi7,
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[25_000_000.0, 25_000_000.0, 25_000_000.0, 25_000_000.0]
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);
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// Setup ethernet pins
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setup_ethernet_pins(
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gpioa.pa1, gpioa.pa2, gpioc.pc1, gpioa.pa7, gpioc.pc4,
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gpioc.pc5, gpiog.pg11, gpiog.pg13, gpiob.pb13
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);
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// Initialise ethernet...
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assert_eq!(ccdr.clocks.hclk().0, 200_000_000); // HCLK 200MHz
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assert_eq!(ccdr.clocks.pclk1().0, 100_000_000); // PCLK 100MHz
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assert_eq!(ccdr.clocks.pclk2().0, 100_000_000); // PCLK 100MHz
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assert_eq!(ccdr.clocks.pclk4().0, 100_000_000); // PCLK 100MHz
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let mac_addr = smoltcp::wire::EthernetAddress::from_bytes(&MAC_ADDRESS);
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let (_eth_dma, mut eth_mac) = unsafe {
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ethernet::new_unchecked(
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dp.ETHERNET_MAC,
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dp.ETHERNET_MTL,
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dp.ETHERNET_DMA,
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&mut DES_RING,
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mac_addr.clone(),
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)
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};
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unsafe {
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ethernet::enable_interrupt();
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cp.NVIC.set_priority(stm32::Interrupt::ETH, 196); // Mid prio
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cortex_m::peripheral::NVIC::unmask(stm32::Interrupt::ETH);
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}
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// ----------------------------------------------------------
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// Begin periodic tasks
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systick_init(&mut delay.free(), ccdr.clocks);
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unsafe {
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cp.SCB.shpr[15 - 4].write(128);
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} // systick exception priority
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// ----------------------------------------------------------
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// Main application loop
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// Setup addresses, maybe not MAC?
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// MAC is set up in prior
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let local_addr = IpAddress::v4(192, 168, 1, 200);
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let mut ip_addrs = [IpCidr::new(local_addr, 24)];
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// let neighbor_cache = NeighborCache::new(BTreeMap::new());
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let mut neighbor_storage = [None; 16];
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let neighbor_cache = NeighborCache::new(&mut neighbor_storage[..]);
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// Device? _eth_dma, as it implements phy::device
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let mut iface = EthernetInterfaceBuilder::new(_eth_dma)
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.ethernet_addr(mac_addr)
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.neighbor_cache(neighbor_cache)
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.ip_addrs(&mut ip_addrs[..])
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.finalize();
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// SCPI configs: migrated to scpi.rs, not meant to be touched
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let tree = scpi_tree!();
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// Device was declared in prior
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let mut errors = ArrayErrorQueue::<[Error; 10]>::new();
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let mut context = Context::new(&mut urukul, &mut errors, tree);
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//Response bytebuffer
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let mut buf = ArrayVecFormatter::<[u8; 256]>::new();
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// SCPI configs END
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// TCP socket buffers
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let mut rx_storage = [0; BUFFER_SIZE];
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let mut tx_storage = [0; BUFFER_SIZE];
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// Setup TCP sockets
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let tcp1_rx_buffer = TcpSocketBuffer::new(&mut rx_storage[..]);
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let tcp1_tx_buffer = TcpSocketBuffer::new(&mut tx_storage[..]);
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let mut tcp1_socket = TcpSocket::new(tcp1_rx_buffer, tcp1_tx_buffer);
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// Setup a silent socket
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let mut silent_rx_storage = [0; BUFFER_SIZE];
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let mut silent_tx_storage = [0; BUFFER_SIZE];
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let silent_rx_buffer = TcpSocketBuffer::new(&mut silent_rx_storage[..]);
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let silent_tx_buffer = TcpSocketBuffer::new(&mut silent_tx_storage[..]);
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let mut silent_socket = TcpSocket::new(silent_rx_buffer, silent_tx_buffer);
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// Socket storage
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let mut sockets_storage = [ None, None ];
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let mut sockets = SocketSet::new(&mut sockets_storage[..]);
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let tcp1_handle = sockets.add(tcp1_socket);
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let silent_handle = sockets.add(silent_socket);
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let mut handles: [SocketHandle; SOCKET_COUNT] = unsafe {
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uninitialized()
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};
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let mut eth_up = false;
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loop {
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let _time = TIME.load(Ordering::Relaxed);
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let eth_last = eth_up;
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match iface.poll(&mut sockets, Instant::from_millis(_time as i64)) {
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Ok(_) => {
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eth_up = true;
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},
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Err(e) => {
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eth_up = false;
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},
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};
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// SCPI interaction socket (:7000)
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{
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let mut socket = sockets.get::<TcpSocket>(silent_handle);
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if !socket.is_open() {
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socket.listen(7000).unwrap();
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socket.set_timeout(Some(Duration::from_millis(1000000)));
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}
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if socket.can_recv() {
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let data = socket.recv(|buffer| {
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(buffer.len(), buffer)
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}).unwrap();
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if str::from_utf8(data).unwrap().trim() == "quit" {
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socket.close();
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socket.abort();
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continue;
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}
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let result = context.run(data, &mut buf);
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if let Err(err) = result {
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writeln!(socket, "{}", str::from_utf8(err.get_message()).unwrap()).unwrap();
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} else {
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write!(socket, "{}", str::from_utf8(buf.as_slice()).unwrap()).unwrap();
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}
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}
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}
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}
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}
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use stm32h7xx_hal::gpio::{
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gpioa::{PA1, PA2, PA7},
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gpiob::{PB13},
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gpioc::{PC1, PC4, PC5},
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gpiog::{PG11, PG13},
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Speed::VeryHigh,
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};
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/*
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* Migrated ethernet setup pins
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*/
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#[allow(non_camel_case_types)]
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pub fn setup_ethernet_pins<REF_CLK, MDIO, MDC, CRS_DV, RXD0, RXD1, TX_EN, TXD0, TXD1>(
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pa1: PA1<REF_CLK>, pa2: PA2<MDIO>, pc1: PC1<MDC>, pa7: PA7<CRS_DV>, pc4: PC4<RXD0>,
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pc5: PC5<RXD1>, pg11: PG11<TX_EN>, pg13: PG13<TXD0>, pb13: PB13<TXD1>
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) {
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pa1.into_alternate_af11().set_speed(VeryHigh);
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pa2.into_alternate_af11().set_speed(VeryHigh);
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pc1.into_alternate_af11().set_speed(VeryHigh);
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pa7.into_alternate_af11().set_speed(VeryHigh);
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pc4.into_alternate_af11().set_speed(VeryHigh);
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pc5.into_alternate_af11().set_speed(VeryHigh);
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pg11.into_alternate_af11().set_speed(VeryHigh);
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pg13.into_alternate_af11().set_speed(VeryHigh);
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pb13.into_alternate_af11().set_speed(VeryHigh);
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}
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#[interrupt]
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fn ETH() {
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unsafe { ethernet::interrupt_handler() }
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}
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#[exception]
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fn SysTick() {
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TIME.fetch_add(1, Ordering::Relaxed);
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}
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#[exception]
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fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! {
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panic!("HardFault at {:#?}", ef);
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}
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#[exception]
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fn DefaultHandler(irqn: i16) {
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panic!("Unhandled exception (IRQn = {})", irqn);
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}
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