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migen: changed eem port

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occheung 2020-08-12 17:34:50 +08:00
parent fe47cafb93
commit cbe36e336d
1 changed files with 1 additions and 1 deletions
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migen/fpga_config.py
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@ -4,7 +4,7 @@ from migen.fhdl.module import Module
class UrukulConnector(Module): class UrukulConnector(Module):
def __init__(self, platform): def __init__(self, platform):
# Request EEM I/O & SPI # Request EEM I/O & SPI
eem = platform.request("eem", 1) eem = platform.request("eem", 0)
spi = platform.request("spi") spi = platform.request("spi")
# Assert signal length # Assert signal length