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urukul: add commented code, but with lifetime conflict

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occheung 2020-08-31 12:32:39 +08:00
parent 49594dfb3b
commit b0272a6fc2
1 changed files with 60 additions and 10 deletions
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68
src/lib.rs
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@ -16,13 +16,14 @@ use cortex_m_semihosting::hprintln;
pub mod bitmask_macro; pub mod bitmask_macro;
pub mod spi_slave; pub mod spi_slave;
// use crate::spi_slave::{ use crate::spi_slave::{
// Parts, Parts,
// SPISlave, SPISlave,
// }; };
pub mod cpld; pub mod cpld;
use crate::cpld::CPLD; use crate::cpld::CPLD;
use crate::cpld::DoOnGetRefMutData;
pub mod config_register; pub mod config_register;
use crate::config_register::ConfigRegister; use crate::config_register::ConfigRegister;
@ -63,12 +64,9 @@ where
{ {
/* /*
* Master constructor for the entire Urukul device * Master constructor for the entire Urukul device
* Supply 7 SPI channels to Urukul and 4 reference clock frequencies
*/ */
pub fn new(spi1: SPI, spi2: SPI, spi3: SPI, spi4: SPI, spi5: SPI, spi6: SPI, spi7: SPI, f_ref_clks: [u64; 4]) -> Self { pub fn new(spi1: SPI, spi2: SPI, spi3: SPI, spi4: SPI, spi5: SPI, spi6: SPI, spi7: SPI, f_ref_clks: [u64; 4]) -> Self {
// Construct cpld and get parts
// let switch = CPLD::new(spi, chip_select, io_update);
// let parts = switch.split();
// Construct Urukul // Construct Urukul
Urukul { Urukul {
config_register: ConfigRegister::new(spi1), config_register: ConfigRegister::new(spi1),
@ -79,7 +77,59 @@ where
DDS::new(spi6, f_ref_clks[2]), DDS::new(spi6, f_ref_clks[2]),
DDS::new(spi7, f_ref_clks[3]), DDS::new(spi7, f_ref_clks[3]),
], ],
// _phantom: PhantomData,
} }
} }
} }
// /*
// * Struct for a better Urukul master device
// */
// pub struct BetterUrukul<'a, SPI, CS0, CS1, CS2, GPIO> {
// cpld: CPLD<SPI, CS0, CS1, CS2, GPIO>,
// parts: Option<Parts<'a, CPLD<SPI, CS0, CS1, CS2, GPIO>, SPI, CS0, CS1, CS2, GPIO>>,
// config_register: Option<ConfigRegister<SPISlave<'a, CPLD<SPI, CS0, CS1, CS2, GPIO>, SPI, CS0, CS1, CS2, GPIO>>>,
// attenuator: Option<Attenuator<SPISlave<'a, CPLD<SPI, CS0, CS1, CS2, GPIO>, SPI, CS0, CS1, CS2, GPIO>>>,
// dds: [Option<DDS<SPISlave<'a, CPLD<SPI, CS0, CS1, CS2, GPIO>, SPI, CS0, CS1, CS2, GPIO>>>; 4],
// }
// impl<'a, SPI, CS0, CS1, CS2, GPIO> BetterUrukul<'a, SPI, CS0, CS1, CS2, GPIO>
// where
// SPI: Transfer<u8>,
// CS0: OutputPin,
// CS1: OutputPin,
// CS2: OutputPin,
// GPIO: OutputPin,
// {
// pub fn new(spi: SPI, chip_select: (CS0, CS1, CS2), io_update: GPIO) -> Self {
// // let switch = CPLD::new(spi, chip_select, io_update);
// // let parts = switch.split();
// // Construct Urukul
// BetterUrukul {
// cpld: CPLD::new(spi, chip_select, io_update),
// // parts: CPLD::new(spi, chip_select, io_update).split(),
// // config_register: ConfigRegister::new(self.parts.spi1),
// // attenuator: Attenuator::new(self.parts.spi2),
// // dds: [
// // DDS::new(self.parts.spi4, f_ref_clks[1]),
// // DDS::new(self.parts.spi5, f_ref_clks[1]),
// // DDS::new(self.parts.spi6, f_ref_clks[2]),
// // DDS::new(self.parts.spi7, f_ref_clks[3]),
// // ],
// parts: None,
// config_register: None,
// attenuator: None,
// dds: [None, None, None, None],
// }
// }
// pub fn init(&'a mut self, f_ref_clks:[u64; 4]) {
// self.parts = Some(self.cpld.split());
// self.config_register = Some(ConfigRegister::new(self.parts.unwrap().spi1));
// self.attenuator = Some(Attenuator::new(self.parts.unwrap().spi2));
// self.dds[0] = Some(DDS::new(self.parts.unwrap().spi4, f_ref_clks[0]));
// self.dds[1] = Some(DDS::new(self.parts.unwrap().spi5, f_ref_clks[1]));
// self.dds[2] = Some(DDS::new(self.parts.unwrap().spi6, f_ref_clks[2]));
// self.dds[3] = Some(DDS::new(self.parts.unwrap().spi7, f_ref_clks[3]));
// }
// }