From 6ef122c9a1dcaeb534a9a14b0f87e9b79c789ae6 Mon Sep 17 00:00:00 2001 From: occheung Date: Sun, 23 Aug 2020 17:17:09 +0800 Subject: [PATCH] migen: beaufity eem res struct --- .cargo/config | 2 +- migen/fpga_config.py | 65 ++++++++++++++++++-------------------------- src/main.rs | 40 ++++++++++++++++++--------- 3 files changed, 55 insertions(+), 52 deletions(-) diff --git a/.cargo/config b/.cargo/config index 86b3292..c0ce242 100644 --- a/.cargo/config +++ b/.cargo/config @@ -1,5 +1,5 @@ [target.thumbv7em-none-eabihf] -runner = "gdb -q -x gdb_config/openocd.gdb" +runner = "gdb -q -x gdb_config/fpga_config.gdb" rustflags = [ "-C", "link-arg=-Tlink.x", ] diff --git a/migen/fpga_config.py b/migen/fpga_config.py index e36cb8d..685c307 100644 --- a/migen/fpga_config.py +++ b/migen/fpga_config.py @@ -10,72 +10,61 @@ from migen.genlib.io import DifferentialInput class UrukulConnector(Module): def __init__(self, platform): # Request EEM I/O & SPI -# eem = platform.request("eem", 0) - eem0 = platform.request("eem0", 0); - eem1 = platform.request("eem0", 1); -# eem2 = platform.request("eem0", 2); - eem2 = platform.request("eem0_n", 2); -# _ignore_eem2 = platform.request("eem0_n", 2); -# miso = platform.request("miso", 0); - eem3 = platform.request("eem0", 3); - eem4 = platform.request("eem0", 4); - eem5 = platform.request("eem0", 5); + eem0 = [ + platform.request("eem0", 0), + platform.request("eem0", 1), + platform.request("eem0_n", 2), + platform.request("eem0", 3), + platform.request("eem0", 4), + platform.request("eem0", 5) + ] spi = platform.request("spi") led = platform.request("user_led") - # Assert signal length - # TODO: Refactor assertion + # Assert SPI resource length assert len(spi.sclk) == 1 assert len(spi.mosi) == 1 -# assert len(spi.miso) == 1 + assert len(spi.miso) == 1 assert len(spi.cs) == 3 - # Flip positive signal as negative output, maybe only do it for FPGA outputs - # self.comb += eem.n.eq(~eem.p) - self.miso_n = Signal() - self.sdo = Signal() + # TODO: Assert EEM resources + assert isinstance(eem0, list) + # Flip positive signal as negative output, maybe only do it for FPGA outputs + self.miso_n = Signal() + + # Very similar setup to Diff setup for iCE40 suggested, but gave B pin instead self.specials += Instance("SB_IO", p_PIN_TYPE=C(0b000001, 6), p_IO_STANDARD="SB_LVDS_INPUT", - io_PACKAGE_PIN=eem2, - i_D_OUT_0=self.sdo, + io_PACKAGE_PIN=eem0[2], o_D_IN_0=self.miso_n ) -# self.submodules += LatticeiCE40DifferentialInputImpl(eem2.p, eem2.n, spi.miso) -# self.specials += DifferentialInput(eem2, None, spi.miso) - # Link EEM to SPI self.comb += [ - eem0.p.eq(spi.sclk), - eem0.n.eq(~spi.sclk), + eem0[0].p.eq(spi.sclk), + eem0[0].n.eq(~spi.sclk), - eem1.p.eq(spi.mosi), - eem1.n.eq(~spi.mosi), + eem0[1].p.eq(spi.mosi), + eem0[1].n.eq(~spi.mosi), -# spi.miso.eq(eem2.p), spi.miso.eq(~self.miso_n), - eem3.p.eq(spi.cs[0]), - eem3.n.eq(~spi.cs[0]), + eem0[3].p.eq(spi.cs[0]), + eem0[3].n.eq(~spi.cs[0]), - eem4.p.eq(spi.cs[1]), - eem4.n.eq(~spi.cs[1]), + eem0[4].p.eq(spi.cs[1]), + eem0[4].n.eq(~spi.cs[1]), - eem5.p.eq(spi.cs[2]), - eem5.n.eq(~spi.cs[2]), + eem0[5].p.eq(spi.cs[2]), + eem0[5].n.eq(~spi.cs[2]), led.eq(1) ] - - # Debug purposes: Tie EEM MISO to EEM MOSI - # self.comb += eem.p[2].eq(eem.p[1]) - - if __name__ == "__main__": platform = HumpbackPlatform() platform.build(UrukulConnector(platform)) diff --git a/src/main.rs b/src/main.rs index 95477e5..31ecd9d 100644 --- a/src/main.rs +++ b/src/main.rs @@ -24,6 +24,7 @@ use firmware::{ config_register::{ ConfigRegister, CFGMask, + StatusMask, }, dds::DDS, }; @@ -99,27 +100,40 @@ fn main() -> ! { let mut config = ConfigRegister::new(parts.spi1); let mut att = Attenuator::new(parts.spi2); + let mut dds0 = DDS::new(parts.spi4); loop { -// let mut counter = config.get_configuration(CFGMask::RF_SW); -// hprintln!("{}", counter); -// config.set_configurations(&mut [ -// (CFGMask::RF_SW, ((counter + 1)%16) as u32) -// ]).unwrap(); - hprintln!("{:?}", att.set_attenuation([33.0, -1.0, 24.0, 12.0]).unwrap()).unwrap(); - hprintln!("{:?}", att.set_attenuation([0.0, 0.0, 0.0, 0.0]).unwrap()).unwrap(); + let mut counter = config.get_status(StatusMask::RF_SW).unwrap(); + hprintln!("{}", counter); + config.set_configurations(&mut [ + (CFGMask::RF_SW, ((counter + 1)%16) as u32) + ]).unwrap(); } /* cs0.set_low().unwrap(); cs1.set_low().unwrap(); cs2.set_low().unwrap(); - - let mut arr: [u8; 4] = [0x12, 0x34, 0x56, 0x78]; + + cs2.set_high().unwrap(); + let mut arr: [u8; 5] = [0x00, 0x00, 0x00, 0x00, 0x02]; + hprintln!("Feedback of conf: {:?}", spi.transfer(&mut arr).unwrap()).unwrap(); + cs2.set_low().unwrap(); + + arr[0] = 0x80; + arr[1] = 0; + arr[2] = 0; + arr[3] = 0; + arr[4] = 0; + cs1.set_high().unwrap(); + hprintln!("first proper feedback: {:?}", spi.transfer(&mut arr).unwrap()).unwrap(); + cs1.set_low().unwrap(); + loop { - arr[0] = 0x12; - arr[1] = 0x34; - arr[2] = 0x56; - arr[3] = 0x78; + arr[0] = 0x81; + arr[1] = 0; + arr[2] = 0; + arr[3] = 0; + arr[4] = 0; cs1.set_high().unwrap(); hprintln!("{:?}", spi.transfer(&mut arr).unwrap()).unwrap(); cs1.set_low().unwrap();