forked from M-Labs/humpback-dds
cpld: fix indent
This commit is contained in:
parent
4852fc54ea
commit
69761c4517
270
src/cpld.rs
270
src/cpld.rs
@ -11,155 +11,155 @@ use core::cell;
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/*
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/*
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* Basic structure for CPLD signal multiplexing
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* Basic structure for CPLD signal multiplexing
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*/
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*/
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#[derive(Debug)]
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#[derive(Debug)]
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pub struct CPLDData<SPI, CS0, CS1, CS2, GPIO> {
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pub struct CPLDData<SPI, CS0, CS1, CS2, GPIO> {
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pub(crate) spi: SPI,
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pub(crate) spi: SPI,
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pub(crate) chip_select: (CS0, CS1, CS2),
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pub(crate) chip_select: (CS0, CS1, CS2),
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pub(crate) io_update: GPIO,
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pub(crate) io_update: GPIO,
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}
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}
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#[derive(Debug)]
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#[derive(Debug)]
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pub struct CPLD<SPI, CS0, CS1, CS2, GPIO> {
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pub struct CPLD<SPI, CS0, CS1, CS2, GPIO> {
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pub(crate) data: cell::RefCell<CPLDData<SPI, CS0, CS1, CS2, GPIO>>,
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pub(crate) data: cell::RefCell<CPLDData<SPI, CS0, CS1, CS2, GPIO>>,
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}
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}
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pub trait SelectChip {
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pub trait SelectChip {
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type Error;
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type Error;
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fn select_chip(&mut self, chip: u8) -> Result<(), Self::Error>;
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fn select_chip(&mut self, chip: u8) -> Result<(), Self::Error>;
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}
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}
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impl<SPI, CS0, CS1, CS2, GPIO, E> SelectChip for CPLDData<SPI, CS0, CS1, CS2, GPIO>
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impl<SPI, CS0, CS1, CS2, GPIO, E> SelectChip for CPLDData<SPI, CS0, CS1, CS2, GPIO>
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where
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where
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SPI: Transfer<u8, Error = E>,
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SPI: Transfer<u8, Error = E>,
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CS0: OutputPin,
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CS0: OutputPin,
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CS1: OutputPin,
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CS1: OutputPin,
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CS2: OutputPin,
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CS2: OutputPin,
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GPIO: OutputPin,
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GPIO: OutputPin,
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{
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{
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type Error = Error<E>;
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type Error = Error<E>;
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fn select_chip(&mut self, chip: u8) -> Result<(), Self::Error> {
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fn select_chip(&mut self, chip: u8) -> Result<(), Self::Error> {
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match chip & (1 << 0) {
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match chip & (1 << 0) {
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0 => self.chip_select.0.set_low(),
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0 => self.chip_select.0.set_low(),
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_ => self.chip_select.0.set_high(),
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_ => self.chip_select.0.set_high(),
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}.map_err(|_| Error::CSError)?;
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}.map_err(|_| Error::CSError)?;
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match chip & (1 << 1) {
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match chip & (1 << 1) {
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0 => self.chip_select.1.set_low(),
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0 => self.chip_select.1.set_low(),
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_ => self.chip_select.1.set_high(),
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_ => self.chip_select.1.set_high(),
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}.map_err(|_| Error::CSError)?;
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}.map_err(|_| Error::CSError)?;
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match chip & (1 << 2) {
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match chip & (1 << 2) {
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0 => self.chip_select.2.set_low(),
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0 => self.chip_select.2.set_low(),
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_ => self.chip_select.2.set_high(),
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_ => self.chip_select.2.set_high(),
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}.map_err(|_| Error::CSError)?;
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}.map_err(|_| Error::CSError)?;
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Ok(())
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Ok(())
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}
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}
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}
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}
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pub trait IssueIOUpdate {
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pub trait IssueIOUpdate {
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type Error;
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type Error;
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fn issue_io_update(&mut self) -> Result<(), Self::Error>;
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fn issue_io_update(&mut self) -> Result<(), Self::Error>;
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}
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}
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impl<SPI, CS0, CS1, CS2, GPIO, E> IssueIOUpdate for CPLDData<SPI, CS0, CS1, CS2, GPIO>
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impl<SPI, CS0, CS1, CS2, GPIO, E> IssueIOUpdate for CPLDData<SPI, CS0, CS1, CS2, GPIO>
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where
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where
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SPI: Transfer<u8>,
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SPI: Transfer<u8>,
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CS0: OutputPin,
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CS0: OutputPin,
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CS1: OutputPin,
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CS1: OutputPin,
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CS2: OutputPin,
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CS2: OutputPin,
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GPIO: OutputPin<Error = E>,
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GPIO: OutputPin<Error = E>,
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{
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{
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type Error = Error<E>;
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type Error = Error<E>;
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fn issue_io_update(&mut self) -> Result<(), Self::Error> {
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fn issue_io_update(&mut self) -> Result<(), Self::Error> {
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self.io_update.set_high().map_err(|_| Error::IOUpdateError)?;
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self.io_update.set_high().map_err(|_| Error::IOUpdateError)?;
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self.io_update.set_low().map_err(|_| Error::IOUpdateError)
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self.io_update.set_low().map_err(|_| Error::IOUpdateError)
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}
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}
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}
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}
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pub trait DoOnGetRefMutData<SPI, CS0, CS1, CS2, GPIO> {
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pub trait DoOnGetRefMutData<SPI, CS0, CS1, CS2, GPIO> {
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fn do_on_get_ref_mut_data<R, E>(
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fn do_on_get_ref_mut_data<R, E>(
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&self,
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&self,
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f: impl FnOnce(cell::RefMut<CPLDData<SPI, CS0, CS1, CS2, GPIO>>) -> Result<R, Error<E>>,
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f: impl FnOnce(cell::RefMut<CPLDData<SPI, CS0, CS1, CS2, GPIO>>) -> Result<R, Error<E>>,
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) -> Result<R, Error<E>>;
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) -> Result<R, Error<E>>;
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}
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}
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impl<SPI, CS0, CS1, CS2, GPIO> DoOnGetRefMutData<SPI, CS0, CS1, CS2, GPIO> for CPLD<SPI, CS0, CS1, CS2, GPIO> {
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impl<SPI, CS0, CS1, CS2, GPIO> DoOnGetRefMutData<SPI, CS0, CS1, CS2, GPIO> for CPLD<SPI, CS0, CS1, CS2, GPIO> {
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fn do_on_get_ref_mut_data<R, E>(
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fn do_on_get_ref_mut_data<R, E>(
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&self,
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&self,
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f: impl FnOnce(cell::RefMut<CPLDData<SPI, CS0, CS1, CS2, GPIO>>) -> Result<R, Error<E>>,
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f: impl FnOnce(cell::RefMut<CPLDData<SPI, CS0, CS1, CS2, GPIO>>) -> Result<R, Error<E>>,
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) -> Result<R, Error<E>> {
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) -> Result<R, Error<E>> {
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let dev = self
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let dev = self
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.data
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.data
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.try_borrow_mut()
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.try_borrow_mut()
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.map_err(|_| Error::GetRefMutDataError)?;
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.map_err(|_| Error::GetRefMutDataError)?;
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f(dev)
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f(dev)
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}
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}
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}
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}
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impl<SPI, CS0, CS1, CS2, GPIO, E> Transfer<u8> for CPLD<SPI, CS0, CS1, CS2, GPIO>
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impl<SPI, CS0, CS1, CS2, GPIO, E> Transfer<u8> for CPLD<SPI, CS0, CS1, CS2, GPIO>
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where
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where
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SPI: Transfer<u8, Error = E>,
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SPI: Transfer<u8, Error = E>,
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CS0: OutputPin,
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CS0: OutputPin,
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CS1: OutputPin,
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CS1: OutputPin,
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CS2: OutputPin,
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CS2: OutputPin,
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GPIO: OutputPin,
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GPIO: OutputPin,
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{
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{
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type Error = Error<E>;
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type Error = Error<E>;
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fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
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fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
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self.do_on_get_ref_mut_data(move |mut dev| dev.spi.transfer(words).map_err(Error::SPI))
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self.do_on_get_ref_mut_data(move |mut dev| dev.spi.transfer(words).map_err(Error::SPI))
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}
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}
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}
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}
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impl<SPI, CS0, CS1, CS2, GPIO, E> CPLD<SPI, CS0, CS1, CS2, GPIO> where
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impl<SPI, CS0, CS1, CS2, GPIO, E> CPLD<SPI, CS0, CS1, CS2, GPIO> where
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SPI: Transfer<u8, Error = E>,
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SPI: Transfer<u8, Error = E>,
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CS0: OutputPin,
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CS0: OutputPin,
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CS1: OutputPin,
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CS1: OutputPin,
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CS2: OutputPin,
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CS2: OutputPin,
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GPIO: OutputPin
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GPIO: OutputPin
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{
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{
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// Constructor for CPLD
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// Constructor for CPLD
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pub fn new(spi: SPI, chip_select: (CS0, CS1, CS2), io_update: GPIO) -> Self {
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pub fn new(spi: SPI, chip_select: (CS0, CS1, CS2), io_update: GPIO) -> Self {
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// Init data
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// Init data
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let data = CPLDData {
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let data = CPLDData {
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spi,
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spi,
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chip_select,
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chip_select,
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io_update,
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io_update,
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};
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};
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// Init CPLD
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// Init CPLD
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CPLD {
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CPLD {
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data: cell::RefCell::new(data),
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data: cell::RefCell::new(data),
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}
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}
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}
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}
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// Destroy the wrapper, return the CPLD data
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// Destroy the wrapper, return the CPLD data
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pub fn destroy(self) -> (SPI, (CS0, CS1, CS2), GPIO) {
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pub fn destroy(self) -> (SPI, (CS0, CS1, CS2), GPIO) {
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let cpld = self.data.into_inner();
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let cpld = self.data.into_inner();
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(cpld.spi, cpld.chip_select, cpld.io_update)
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(cpld.spi, cpld.chip_select, cpld.io_update)
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}
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}
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// Split SPI into chips, wrapped by Parts struct
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// Split SPI into chips, wrapped by Parts struct
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pub fn split<'a>(&'a self) -> Parts<'a, CPLD<SPI, CS0, CS1, CS2, GPIO>, SPI, CS0, CS1, CS2, GPIO> {
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pub fn split<'a>(&'a self) -> Parts<'a, CPLD<SPI, CS0, CS1, CS2, GPIO>, SPI, CS0, CS1, CS2, GPIO> {
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Parts::new(&self)
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Parts::new(&self)
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}
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}
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// Select Chip
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// Select Chip
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pub fn select_chip(&mut self, channel: u8) -> Result<(), Error<E>> {
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pub fn select_chip(&mut self, channel: u8) -> Result<(), Error<E>> {
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self.do_on_get_ref_mut_data(|mut dev| dev.select_chip(channel))
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self.do_on_get_ref_mut_data(|mut dev| dev.select_chip(channel))
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}
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}
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}
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}
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impl<SPI, CS0, CS1, CS2, GPIO, E> CPLD<SPI, CS0, CS1, CS2, GPIO>
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impl<SPI, CS0, CS1, CS2, GPIO, E> CPLD<SPI, CS0, CS1, CS2, GPIO>
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where
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where
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SPI: Transfer<u8>,
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SPI: Transfer<u8>,
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CS0: OutputPin,
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CS0: OutputPin,
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CS1: OutputPin,
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CS1: OutputPin,
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CS2: OutputPin,
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CS2: OutputPin,
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GPIO: OutputPin<Error = E>
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GPIO: OutputPin<Error = E>
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{
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{
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// Issue I/O Update
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// Issue I/O Update
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pub fn issue_io_update(&mut self) -> Result<(), Error<E>> {
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pub fn issue_io_update(&mut self) -> Result<(), Error<E>> {
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self.do_on_get_ref_mut_data(|mut dev| dev.issue_io_update())
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self.do_on_get_ref_mut_data(|mut dev| dev.issue_io_update())
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}
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}
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}
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}
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