From 49c5fec30f0db827d162220ce00cbe913f3912e9 Mon Sep 17 00:00:00 2001 From: occheung Date: Wed, 27 Jan 2021 15:56:46 +0800 Subject: [PATCH] Bug fixes: + Manage I/O Update pulse width. - Remove retry-till-success PLL setup. * Filter away unused bit in ASF when reading from DDS * Reduce log from SPI --- src/cpld.rs | 5 +++++ src/dds.rs | 2 +- src/logger.rs | 2 +- src/urukul.rs | 13 +------------ 4 files changed, 8 insertions(+), 14 deletions(-) diff --git a/src/cpld.rs b/src/cpld.rs index 0429693..3f00e5a 100644 --- a/src/cpld.rs +++ b/src/cpld.rs @@ -49,6 +49,11 @@ where pub(crate) fn issue_io_update(&mut self) -> Result<(), Error> { self.io_update.set_high().map_err(|_| Error::IOUpdateError)?; + // I/O Update minimum pulse width: 1 SYNC_CLK cycle + // 1 SYNC_CLK cycle = 4 REF_CLK cycle, where f_ref_clk is at least 3.2 MHz + // Therefore the maximum required pulse length is 1.25 us, + // equivalent to 500 cycles with STM32 sysclk at 400 MHz, longer delay is provided. + cortex_m::asm::delay(1_000); self.io_update.set_low().map_err(|_| Error::IOUpdateError) } } diff --git a/src/dds.rs b/src/dds.rs index 550b039..1b49472 100644 --- a/src/dds.rs +++ b/src/dds.rs @@ -411,7 +411,7 @@ where (profile_content[3] as u64); let phase: f64 = ((pow as f64)/(((1_u64) << 16) as f64))*360.0; - let asf: u64 = (profile_content[0] as u64) << 8 | + let asf: u64 = ((profile_content[0] & 0x3F) as u64) << 8 | (profile_content[1] as u64); let amplitude: f64 = (asf as f64)/(((1_u64) << 14) as f64); diff --git a/src/logger.rs b/src/logger.rs index 76e1784..b277fe9 100644 --- a/src/logger.rs +++ b/src/logger.rs @@ -64,7 +64,7 @@ use cortex_m_log::{ lazy_static! { static ref LOGGER: Logger> = Logger { - level: LevelFilter::Trace, + level: LevelFilter::Info, inner: unsafe { InterruptSync::new( ItmDest::new(cortex_m::Peripherals::steal().ITM) diff --git a/src/urukul.rs b/src/urukul.rs index 101d6b1..9ca3cdf 100644 --- a/src/urukul.rs +++ b/src/urukul.rs @@ -340,18 +340,7 @@ where } pub fn set_channel_sys_clk(&mut self, channel: u8, f_sys_clk: f64) -> Result<(), Error> { - loop { - if let Err(e) = self.dds[usize::from(channel)].set_sys_clk_frequency(f_sys_clk).map(|_| ()) { - if e.is_wait_retry() { - cortex_m::asm::delay(400_000); - } else { - return Err(e); - } - } else { - break; - } - } - Ok(()) + self.dds[usize::from(channel)].set_sys_clk_frequency(f_sys_clk) } pub fn get_channel_sys_clk(&mut self, channel: u8) -> Result> {