forked from M-Labs/nac3
kasli_soc & zc706: Fix GTX Clock Path during INIT
This commit is contained in:
parent
e6372b9766
commit
e1b2c45813
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@ -237,12 +237,16 @@ class GenericMaster(SoCCore):
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gtx0 = self.gt_drtio.gtxs[0]
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self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
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ext_async_rst = Signal()
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self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
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self.submodules.sys_crg = zynq_clocking.SYSCRG(
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self.platform,
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self.ps7,
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txout_buf,
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clk_sw=gtx0.tx_init.done)
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clk_sw=self.gt_drtio.stable_clkin.storage,
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clk_sw_status=gtx0.tx_init.done,
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ext_async_rst=ext_async_rst)
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self.csr_devices.append("sys_crg")
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.crg.cd_sys = self.sys_crg.cd_sys
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@ -250,6 +254,9 @@ class GenericMaster(SoCCore):
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self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
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fix_serdes_timing_path(platform)
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self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done)
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self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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@ -419,12 +426,16 @@ class GenericSatellite(SoCCore):
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gtx0 = self.gt_drtio.gtxs[0]
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self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
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ext_async_rst = Signal()
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self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
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self.submodules.sys_crg = zynq_clocking.SYSCRG(
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self.platform,
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self.ps7,
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txout_buf,
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clk_sw=gtx0.tx_init.done)
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clk_sw=self.gt_drtio.stable_clkin.storage,
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clk_sw_status=gtx0.tx_init.done,
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ext_async_rst=ext_async_rst)
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platform.add_false_path_constraints(
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self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
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self.csr_devices.append("sys_crg")
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@ -433,6 +444,9 @@ class GenericSatellite(SoCCore):
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fix_serdes_timing_path(platform)
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self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done)
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self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
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self.rtio_channels = []
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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if has_grabber:
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@ -226,6 +226,7 @@ class _MasterBase(SoCCore):
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self.csr_devices.append("gt_drtio")
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self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
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ext_async_rst = Signal()
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txout_buf = Signal()
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gtx0 = self.gt_drtio.gtxs[0]
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self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
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@ -234,12 +235,17 @@ class _MasterBase(SoCCore):
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self.platform,
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self.ps7,
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txout_buf,
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clk_sw=gtx0.tx_init.done,
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clk_sw=self.gt_drtio.stable_clkin.storage,
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clk_sw_status=gtx0.tx_init.done,
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ext_async_rst=ext_async_rst,
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freq=clk_freq)
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platform.add_false_path_constraints(
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self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
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self.csr_devices.append("sys_crg")
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self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done)
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self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
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drtio_csr_group = []
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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@ -361,6 +367,7 @@ class _SatelliteBase(SoCCore):
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clk_freq=clk_freq)
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self.csr_devices.append("gt_drtio")
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ext_async_rst = Signal()
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txout_buf = Signal()
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txout_buf.attr.add("keep")
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gtx0 = self.gt_drtio.gtxs[0]
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@ -373,12 +380,17 @@ class _SatelliteBase(SoCCore):
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self.platform,
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self.ps7,
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txout_buf,
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clk_sw=gtx0.tx_init.done,
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clk_sw=self.gt_drtio.stable_clkin.storage,
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clk_sw_status=gtx0.tx_init.done,
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ext_async_rst=ext_async_rst,
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freq=clk_freq)
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platform.add_false_path_constraints(
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self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
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self.csr_devices.append("sys_crg")
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self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done)
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self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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drtiorep_csr_group = []
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