forked from M-Labs/nac3
Firmware: Si549 and io_expander
io_expander: set CLK_SEL pin to output when si549 is used io_expander: gate virtual leds for standalone si549: add bit bang i2c si549: add si549 programming si549: add main & helper setup
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7827c7b803
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@ -1,6 +1,7 @@
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use libboard_zynq::i2c;
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use log::info;
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#[cfg(has_virtual_leds)]
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use crate::pl::csr;
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// Only the bare minimum registers. Bits/IO connections equivalent between IC types.
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@ -19,11 +20,15 @@ const IODIR_OUT_SFP_LED: u8 = 0x40;
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const IODIR_OUT_SFP0_LED: u8 = 0x40;
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#[cfg(hw_rev = "v1.1")]
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const IODIR_OUT_SFP0_LED: u8 = 0x80;
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#[cfg(has_si549)]
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const IODIR_CLK_SEL: u8 = 0x80; // out
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#[cfg(has_si5324)]
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const IODIR_CLK_SEL: u8 = 0x00; // in
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//IO expander port direction
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const IODIR0: [u8; 2] = [
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0xFF & !IODIR_OUT_SFP_TX_DISABLE & !IODIR_OUT_SFP0_LED,
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0xFF & !IODIR_OUT_SFP_TX_DISABLE & !IODIR_OUT_SFP_LED,
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0xFF & !IODIR_OUT_SFP_TX_DISABLE & !IODIR_OUT_SFP_LED & !IODIR_CLK_SEL,
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];
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const IODIR1: [u8; 2] = [
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@ -33,6 +38,7 @@ const IODIR1: [u8; 2] = [
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pub struct IoExpander {
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address: u8,
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#[cfg(has_virtual_leds)]
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virtual_led_mapping: &'static [(u8, u8, u8)],
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iodir: [u8; 2],
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out_current: [u8; 2],
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@ -42,17 +48,18 @@ pub struct IoExpander {
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impl IoExpander {
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pub fn new(i2c: &mut i2c::I2c, index: u8) -> Result<Self, &'static str> {
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#[cfg(hw_rev = "v1.0")]
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#[cfg(all(hw_rev = "v1.0", has_virtual_leds))]
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const VIRTUAL_LED_MAPPING0: [(u8, u8, u8); 2] = [(0, 0, 6), (1, 1, 6)];
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#[cfg(hw_rev = "v1.1")]
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#[cfg(all(hw_rev = "v1.1", has_virtual_leds))]
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const VIRTUAL_LED_MAPPING0: [(u8, u8, u8); 2] = [(0, 0, 7), (1, 1, 6)];
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#[cfg(has_virtual_leds)]
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const VIRTUAL_LED_MAPPING1: [(u8, u8, u8); 2] = [(2, 0, 6), (3, 1, 6)];
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// Both expanders on SHARED I2C bus
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let mut io_expander = match index {
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0 => IoExpander {
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address: 0x40,
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#[cfg(has_virtual_leds)]
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virtual_led_mapping: &VIRTUAL_LED_MAPPING0,
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iodir: IODIR0,
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out_current: [0; 2],
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@ -66,6 +73,7 @@ impl IoExpander {
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},
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1 => IoExpander {
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address: 0x42,
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#[cfg(has_virtual_leds)]
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virtual_led_mapping: &VIRTUAL_LED_MAPPING1,
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iodir: IODIR1,
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out_current: [0; 2],
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@ -35,7 +35,8 @@ pub mod drtio_eem;
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pub mod grabber;
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#[cfg(has_si5324)]
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pub mod si5324;
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#[cfg(has_si549)]
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pub mod si549;
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use core::{cmp, str};
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pub fn identifier_read(buf: &mut [u8]) -> &str {
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@ -0,0 +1,326 @@
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use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
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use libboard_zynq::timer::GlobalTimer;
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use log::info;
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use crate::pl::csr;
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#[cfg(feature = "target_kasli_soc")]
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const ADDRESS: u8 = 0x67;
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const ADPLL_MAX: i32 = (950.0 / 0.0001164) as i32;
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pub struct DividerConfig {
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pub hsdiv: u16,
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pub lsdiv: u8,
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pub fbdiv: u64,
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}
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pub struct FrequencySetting {
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pub main: DividerConfig,
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pub helper: DividerConfig,
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}
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mod i2c {
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use super::*;
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#[derive(Clone, Copy)]
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pub enum DCXO {
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Main,
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Helper,
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}
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fn half_period(timer: &mut GlobalTimer) {
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timer.delay_us(1)
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}
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fn sda_i(dcxo: DCXO) -> bool {
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match dcxo {
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DCXO::Main => unsafe { csr::wrpll::main_dcxo_sda_in_read() == 1 },
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DCXO::Helper => unsafe { csr::wrpll::helper_dcxo_sda_in_read() == 1 },
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}
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}
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fn sda_oe(dcxo: DCXO, oe: bool) {
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let val = if oe { 1 } else { 0 };
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match dcxo {
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DCXO::Main => unsafe { csr::wrpll::main_dcxo_sda_oe_write(val) },
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DCXO::Helper => unsafe { csr::wrpll::helper_dcxo_sda_oe_write(val) },
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};
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}
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fn sda_o(dcxo: DCXO, o: bool) {
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let val = if o { 1 } else { 0 };
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match dcxo {
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DCXO::Main => unsafe { csr::wrpll::main_dcxo_sda_out_write(val) },
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DCXO::Helper => unsafe { csr::wrpll::helper_dcxo_sda_out_write(val) },
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};
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}
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fn scl_oe(dcxo: DCXO, oe: bool) {
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let val = if oe { 1 } else { 0 };
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match dcxo {
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DCXO::Main => unsafe { csr::wrpll::main_dcxo_scl_oe_write(val) },
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DCXO::Helper => unsafe { csr::wrpll::helper_dcxo_scl_oe_write(val) },
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};
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}
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fn scl_o(dcxo: DCXO, o: bool) {
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let val = if o { 1 } else { 0 };
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match dcxo {
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DCXO::Main => unsafe { csr::wrpll::main_dcxo_scl_out_write(val) },
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DCXO::Helper => unsafe { csr::wrpll::helper_dcxo_scl_out_write(val) },
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};
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}
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pub fn init(dcxo: DCXO, timer: &mut GlobalTimer) -> Result<(), &'static str> {
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// Set SCL as output, and high level
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scl_o(dcxo, true);
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scl_oe(dcxo, true);
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// Prepare a zero level on SDA so that sda_oe pulls it down
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sda_o(dcxo, false);
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// Release SDA
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sda_oe(dcxo, false);
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// Check the I2C bus is ready
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half_period(timer);
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half_period(timer);
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if !sda_i(dcxo) {
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// Try toggling SCL a few times
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for _bit in 0..8 {
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scl_o(dcxo, false);
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half_period(timer);
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scl_o(dcxo, true);
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half_period(timer);
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}
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}
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if !sda_i(dcxo) {
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return Err("SDA is stuck low and doesn't get unstuck");
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}
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Ok(())
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}
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pub fn start(dcxo: DCXO, timer: &mut GlobalTimer) {
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// Set SCL high then SDA low
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scl_o(dcxo, true);
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half_period(timer);
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sda_oe(dcxo, true);
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half_period(timer);
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}
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pub fn stop(dcxo: DCXO, timer: &mut GlobalTimer) {
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// First, make sure SCL is low, so that the target releases the SDA line
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scl_o(dcxo, false);
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half_period(timer);
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// Set SCL high then SDA high
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sda_oe(dcxo, true);
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scl_o(dcxo, true);
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half_period(timer);
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sda_oe(dcxo, false);
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half_period(timer);
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}
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pub fn write(dcxo: DCXO, data: u8, timer: &mut GlobalTimer) -> bool {
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// MSB first
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for bit in (0..8).rev() {
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// Set SCL low and set our bit on SDA
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scl_o(dcxo, false);
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sda_oe(dcxo, data & (1 << bit) == 0);
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half_period(timer);
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// Set SCL high ; data is shifted on the rising edge of SCL
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scl_o(dcxo, true);
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half_period(timer);
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}
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// Check ack
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// Set SCL low, then release SDA so that the I2C target can respond
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scl_o(dcxo, false);
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half_period(timer);
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sda_oe(dcxo, false);
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// Set SCL high and check for ack
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scl_o(dcxo, true);
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half_period(timer);
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// returns true if acked (I2C target pulled SDA low)
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!sda_i(dcxo)
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}
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pub fn read(dcxo: DCXO, ack: bool, timer: &mut GlobalTimer) -> u8 {
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// Set SCL low first, otherwise setting SDA as input may cause a transition
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// on SDA with SCL high which will be interpreted as START/STOP condition.
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scl_o(dcxo, false);
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half_period(timer); // make sure SCL has settled low
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sda_oe(dcxo, false);
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let mut data: u8 = 0;
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// MSB first
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for bit in (0..8).rev() {
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scl_o(dcxo, false);
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half_period(timer);
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// Set SCL high and shift data
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scl_o(dcxo, true);
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half_period(timer);
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if sda_i(dcxo) {
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data |= 1 << bit
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}
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}
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// Send ack
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// Set SCL low and pull SDA low when acking
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scl_o(dcxo, false);
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if ack {
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sda_oe(dcxo, true)
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}
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half_period(timer);
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// then set SCL high
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scl_o(dcxo, true);
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half_period(timer);
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data
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}
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}
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fn write(dcxo: i2c::DCXO, reg: u8, val: u8, timer: &mut GlobalTimer) -> Result<(), &'static str> {
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i2c::start(dcxo, timer);
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if !i2c::write(dcxo, ADDRESS << 1, timer) {
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return Err("Si549 failed to ack write address");
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}
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if !i2c::write(dcxo, reg, timer) {
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return Err("Si549 failed to ack register");
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}
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if !i2c::write(dcxo, val, timer) {
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return Err("Si549 failed to ack value");
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}
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i2c::stop(dcxo, timer);
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Ok(())
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}
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fn read(dcxo: i2c::DCXO, reg: u8, timer: &mut GlobalTimer) -> Result<u8, &'static str> {
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i2c::start(dcxo, timer);
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if !i2c::write(dcxo, ADDRESS << 1, timer) {
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return Err("Si549 failed to ack write address");
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}
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if !i2c::write(dcxo, reg, timer) {
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return Err("Si549 failed to ack register");
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}
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i2c::stop(dcxo, timer);
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i2c::start(dcxo, timer);
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if !i2c::write(dcxo, (ADDRESS << 1) | 1, timer) {
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return Err("Si549 failed to ack read address");
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}
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let val = i2c::read(dcxo, false, timer);
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i2c::stop(dcxo, timer);
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Ok(val)
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}
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fn setup(dcxo: i2c::DCXO, config: &DividerConfig, timer: &mut GlobalTimer) -> Result<(), &'static str> {
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i2c::init(dcxo, timer)?;
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write(dcxo, 255, 0x00, timer)?; // PAGE
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write(dcxo, 69, 0x00, timer)?; // Disable FCAL override.
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write(dcxo, 17, 0x00, timer)?; // Synchronously disable output
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// The Si549 has no ID register, so we check that it responds correctly
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// by writing values to a RAM-like register and reading them back.
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for test_value in 0..255 {
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write(dcxo, 23, test_value, timer)?;
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let readback = read(dcxo, 23, timer)?;
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if readback != test_value {
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return Err("Si549 detection failed");
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}
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}
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write(dcxo, 23, config.hsdiv as u8, timer)?;
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write(dcxo, 24, (config.hsdiv >> 8) as u8 | (config.lsdiv << 4), timer)?;
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write(dcxo, 26, config.fbdiv as u8, timer)?;
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write(dcxo, 27, (config.fbdiv >> 8) as u8, timer)?;
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write(dcxo, 28, (config.fbdiv >> 16) as u8, timer)?;
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write(dcxo, 29, (config.fbdiv >> 24) as u8, timer)?;
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write(dcxo, 30, (config.fbdiv >> 32) as u8, timer)?;
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write(dcxo, 31, (config.fbdiv >> 40) as u8, timer)?;
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write(dcxo, 7, 0x08, timer)?; // Start FCAL
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timer.delay_us(30_000); // Internal FCAL VCO calibration
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write(dcxo, 17, 0x01, timer)?; // Synchronously enable output
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Ok(())
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}
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pub fn main_setup(timer: &mut GlobalTimer, settings: &FrequencySetting) -> Result<(), &'static str> {
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unsafe {
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csr::wrpll::main_dcxo_bitbang_enable_write(1);
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csr::wrpll::main_dcxo_i2c_address_write(ADDRESS);
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}
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setup(i2c::DCXO::Main, &settings.main, timer)?;
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// Si549 maximum settling time for large frequency change.
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timer.delay_us(40_000);
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unsafe {
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csr::wrpll::main_dcxo_bitbang_enable_write(0);
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}
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info!("Main Si549 started");
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Ok(())
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}
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pub fn helper_setup(timer: &mut GlobalTimer, settings: &FrequencySetting) -> Result<(), &'static str> {
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unsafe {
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csr::wrpll::helper_reset_write(1);
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csr::wrpll::helper_dcxo_bitbang_enable_write(1);
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csr::wrpll::helper_dcxo_i2c_address_write(ADDRESS);
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}
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setup(i2c::DCXO::Helper, &settings.helper, timer)?;
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// Si549 maximum settling time for large frequency change.
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timer.delay_us(40_000);
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unsafe {
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csr::wrpll::helper_reset_write(0);
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csr::wrpll::helper_dcxo_bitbang_enable_write(0);
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}
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info!("Helper Si549 started");
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Ok(())
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}
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fn set_adpll(dcxo: i2c::DCXO, adpll: i32) -> Result<(), &'static str> {
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if adpll.abs() > ADPLL_MAX {
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return Err("adpll is too large");
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}
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match dcxo {
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i2c::DCXO::Main => unsafe {
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if csr::wrpll::main_dcxo_bitbang_enable_read() == 1 {
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return Err("Main si549 bitbang mode is active when using gateware i2c");
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}
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while csr::wrpll::main_dcxo_adpll_busy_read() == 1 {}
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if csr::wrpll::main_dcxo_nack_read() == 1 {
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return Err("Main si549 failed to ack adpll write");
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}
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csr::wrpll::main_dcxo_i2c_address_write(ADDRESS);
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csr::wrpll::main_dcxo_adpll_write(adpll as u32);
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csr::wrpll::main_dcxo_adpll_stb_write(1);
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},
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i2c::DCXO::Helper => unsafe {
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if csr::wrpll::helper_dcxo_bitbang_enable_read() == 1 {
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return Err("Helper si549 bitbang mode is active when using gateware i2c");
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}
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while csr::wrpll::helper_dcxo_adpll_busy_read() == 1 {}
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if csr::wrpll::helper_dcxo_nack_read() == 1 {
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return Err("Helper si549 failed to ack adpll write");
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}
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csr::wrpll::helper_dcxo_i2c_address_write(ADDRESS);
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csr::wrpll::helper_dcxo_adpll_write(adpll as u32);
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csr::wrpll::helper_dcxo_adpll_stb_write(1);
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},
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};
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Ok(())
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}
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