forked from M-Labs/nac3
drtio_aux_controller: support aux_buffer_count
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14fa038118
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92a29051f7
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@ -1,12 +1,12 @@
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"""Auxiliary controller, common to satellite and master"""
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from artiq.gateware.drtio.aux_controller import Transmitter, Receiver
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from artiq.gateware.drtio.aux_controller import (max_packet, aux_buffer_count,
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Transmitter, Receiver)
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from migen.fhdl.simplify import FullMemoryWE
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from misoc.interconnect.csr import *
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from migen_axi.interconnect.sram import SRAM
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from migen_axi.interconnect import axi
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max_packet = 1024
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class _DRTIOAuxControllerBase(Module):
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def __init__(self, link_layer):
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@ -27,12 +27,12 @@ class DRTIOAuxControllerAxi(_DRTIOAuxControllerBase):
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tx_sdram_if = SRAM(self.transmitter.mem, read_only=False)
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rx_sdram_if = SRAM(self.receiver.mem, read_only=True)
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aw_decoder = axi.AddressDecoder(self.bus.aw,
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[(lambda a: a[log2_int(max_packet)] == 0, tx_sdram_if.bus.aw),
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(lambda a: a[log2_int(max_packet)] == 1, rx_sdram_if.bus.aw)],
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[(lambda a: a[log2_int(max_packet*aux_buffer_count)] == 0, tx_sdram_if.bus.aw),
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(lambda a: a[log2_int(max_packet*aux_buffer_count)] == 1, rx_sdram_if.bus.aw)],
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register=True)
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ar_decoder = axi.AddressDecoder(self.bus.ar,
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[(lambda a: a[log2_int(max_packet)] == 0, tx_sdram_if.bus.ar),
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(lambda a: a[log2_int(max_packet)] == 1, rx_sdram_if.bus.ar)],
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[(lambda a: a[log2_int(max_packet*aux_buffer_count)] == 0, tx_sdram_if.bus.ar),
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(lambda a: a[log2_int(max_packet*aux_buffer_count)] == 1, rx_sdram_if.bus.ar)],
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register=True)
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# unlike wb, axi address decoder only connects ar/aw lanes,
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# the rest must also be connected!
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@ -82,4 +82,4 @@ class DRTIOAuxControllerBare(_DRTIOAuxControllerBase):
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return self.receiver.mem.get_port(write_capable=False)
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def get_mem_size(self):
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return max_packet
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return max_packet*aux_buffer_count
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