From 2ddb4d259f809cead6ba57221cb2db23bd39f92d Mon Sep 17 00:00:00 2001 From: David Nadlinger Date: Sat, 17 Dec 2022 01:31:14 +0000 Subject: [PATCH] Undo most of Si5324 unification (5c054cc901) This reverts most of 5c054cc901, as it turns out that si5324::setup is in fact also used to configure the chip for operation as a DRTIO satellite. --- src/libboard_artiq/src/si5324.rs | 5 +- src/runtime/src/rtio_clocking.rs | 171 +++++++++++++++++-------------- 2 files changed, 97 insertions(+), 79 deletions(-) diff --git a/src/libboard_artiq/src/si5324.rs b/src/libboard_artiq/src/si5324.rs index a0b971d8..574fec0b 100644 --- a/src/libboard_artiq/src/si5324.rs +++ b/src/libboard_artiq/src/si5324.rs @@ -219,11 +219,8 @@ pub fn bypass(i2c: &mut I2c, input: Input, timer: &mut GlobalTimer) -> Result<() Ok(()) } -pub fn setup(i2c: &mut I2c, settings: &FrequencySettings, ext_input: Input, timer: &mut GlobalTimer) -> Result<()> { +pub fn setup(i2c: &mut I2c, settings: &FrequencySettings, input: Input, timer: &mut GlobalTimer) -> Result<()> { let s = map_frequency_settings(settings)?; - - // FREE_RUN=1 routes XA/XB to CKIN2. - let input = if settings.crystal_ref { Input::Ckin2 } else { ext_input }; let cksel_reg = match input { Input::Ckin1 => 0b00, Input::Ckin2 => 0b01, diff --git a/src/runtime/src/rtio_clocking.rs b/src/runtime/src/rtio_clocking.rs index 4c32c6f1..8b887575 100644 --- a/src/runtime/src/rtio_clocking.rs +++ b/src/runtime/src/rtio_clocking.rs @@ -121,100 +121,121 @@ const SI5324_EXT_INPUT: si5324::Input = si5324::Input::Ckin1; #[cfg(has_si5324)] fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) { - let si5324_settings = match clk { + let (si5324_settings, si5324_ref_input) = match clk { RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW info!("using 10MHz reference to make 125MHz RTIO clock with PLL"); - si5324::FrequencySettings { - n1_hs : 10, - nc1_ls : 4, - n2_hs : 10, - n2_ls : 300, - n31 : 6, - n32 : 6, - bwsel : 4, - crystal_ref: false - } + ( + si5324::FrequencySettings { + n1_hs : 10, + nc1_ls : 4, + n2_hs : 10, + n2_ls : 300, + n31 : 6, + n32 : 6, + bwsel : 4, + crystal_ref: false + }, + SI5324_EXT_INPUT + ) }, RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth info!("using 100MHz reference to make 125MHz RTIO clock with PLL"); - si5324::FrequencySettings { - n1_hs : 10, - nc1_ls : 4, - n2_hs : 10, - n2_ls : 260, - n31 : 52, - n32 : 52, - bwsel : 4, - crystal_ref: false - } + ( + si5324::FrequencySettings { + n1_hs : 10, + nc1_ls : 4, + n2_hs : 10, + n2_ls : 260, + n31 : 52, + n32 : 52, + bwsel : 4, + crystal_ref: false + }, + SI5324_EXT_INPUT + ) }, RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth info!("using 125MHz reference to make 125MHz RTIO clock with PLL"); - si5324::FrequencySettings { - n1_hs : 5, - nc1_ls : 8, - n2_hs : 7, - n2_ls : 360, - n31 : 63, - n32 : 63, - bwsel : 4, - crystal_ref: false - } + ( + si5324::FrequencySettings { + n1_hs : 5, + nc1_ls : 8, + n2_hs : 7, + n2_ls : 360, + n31 : 63, + n32 : 63, + bwsel : 4, + crystal_ref: false + }, + SI5324_EXT_INPUT + ) }, RtioClock::Int_150 => { // 150MHz output, from crystal info!("using internal 150MHz RTIO clock"); - si5324::FrequencySettings { - n1_hs : 9, - nc1_ls : 4, - n2_hs : 10, - n2_ls : 33732, - n31 : 7139, - n32 : 7139, - bwsel : 3, - crystal_ref: true - } + ( + si5324::FrequencySettings { + n1_hs : 9, + nc1_ls : 4, + n2_hs : 10, + n2_ls : 33732, + n31 : 7139, + n32 : 7139, + bwsel : 3, + crystal_ref: true + }, + si5324::Input::Ckin2 + ) }, RtioClock::Int_100 => { // 100MHz output, from crystal info!("using internal 100MHz RTIO clock"); - si5324::FrequencySettings { - n1_hs : 9, - nc1_ls : 6, - n2_hs : 10, - n2_ls : 33732, - n31 : 7139, - n32 : 7139, - bwsel : 3, - crystal_ref: true - } + ( + si5324::FrequencySettings { + n1_hs : 9, + nc1_ls : 6, + n2_hs : 10, + n2_ls : 33732, + n31 : 7139, + n32 : 7139, + bwsel : 3, + crystal_ref: true + }, + si5324::Input::Ckin2 + ) }, RtioClock::Int_125 => { // 125MHz output, from crystal, 7 Hz info!("using internal 125MHz RTIO clock"); - si5324::FrequencySettings { - n1_hs : 10, - nc1_ls : 4, - n2_hs : 10, - n2_ls : 19972, - n31 : 4565, - n32 : 4565, - bwsel : 4, - crystal_ref: true - } - } - _ => { // 125MHz output like above, default (if chosen option is not supported) - warn!("rtio_clock setting '{:?}' is not supported. Falling back to default internal 125MHz RTIO clock.", clk); - si5324::FrequencySettings { - n1_hs : 10, - nc1_ls : 4, - n2_hs : 10, - n2_ls : 19972, - n31 : 4565, - n32 : 4565, - bwsel : 4, - crystal_ref: true - } + ( + si5324::FrequencySettings { + n1_hs : 10, + nc1_ls : 4, + n2_hs : 10, + n2_ls : 19972, + n31 : 4565, + n32 : 4565, + bwsel : 4, + crystal_ref: true + }, + si5324::Input::Ckin2 + ) + }, + _ => { // same setting as Int_125, but fallback to default + warn!("rtio_clock setting '{:?}' is unsupported. Falling back to default internal 125MHz RTIO clock.", clk); + ( + si5324::FrequencySettings { + n1_hs : 10, + nc1_ls : 4, + n2_hs : 10, + n2_ls : 19972, + n31 : 4565, + n32 : 4565, + bwsel : 4, + crystal_ref: true + }, + si5324::Input::Ckin2 + ) } }; - si5324::setup(i2c, &si5324_settings, SI5324_EXT_INPUT, timer).expect("cannot initialize Si5324"); + si5324::setup(i2c, &si5324_settings, si5324_ref_input, timer).expect("cannot initialize Si5324"); } pub fn init(timer: &mut GlobalTimer, cfg: &Config) {