From 10a12245a3556b3420263103ce012f596c754529 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 16 Jul 2020 17:10:09 +0800 Subject: [PATCH] analyzer: fix endianness issue --- src/gateware/analyzer.py | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/gateware/analyzer.py b/src/gateware/analyzer.py index 6827ae9d..45030fe5 100644 --- a/src/gateware/analyzer.py +++ b/src/gateware/analyzer.py @@ -7,6 +7,15 @@ from migen_axi.interconnect import axi from artiq.gateware.rtio.analyzer import message_len, MessageEncoder +def convert_endianness(signal): + assert len(signal) % 8 == 0 + nbytes = len(signal)//8 + signal_bytes = [] + for i in range(nbytes): + signal_bytes.append(signal[8*i:8*(i+1)]) + return Cat(*reversed(signal_bytes)) + + class AXIDMAWriter(Module, AutoCSR): def __init__(self, membus, max_outstanding_requests): aw = len(membus.aw.addr) @@ -55,7 +64,7 @@ class AXIDMAWriter(Module, AutoCSR): membus.w.id.eq(0), membus.w.valid.eq(self.sink.stb), self.sink.ack.eq(membus.w.ready), - membus.w.data.eq(self.sink.data), + membus.w.data.eq(convert_endianness(self.sink.data)), membus.w.strb.eq(2**(dw//8)-1), ] beat_count = Signal(max=burst_length)