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runtime: encapsulate core1 state in KernelControl

This commit is contained in:
Astro 2020-04-16 23:58:04 +02:00 committed by Sebastien Bourdeauducq
parent c8d779d4cc
commit 105eb7c2bc
3 changed files with 57 additions and 13 deletions

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@ -2,6 +2,7 @@ use core::{mem::transmute, task::Poll};
use core::fmt; use core::fmt;
use core::cmp::min; use core::cmp::min;
use core::cell::RefCell; use core::cell::RefCell;
use alloc::rc::Rc;
use num_derive::{FromPrimitive, ToPrimitive}; use num_derive::{FromPrimitive, ToPrimitive};
use num_traits::{FromPrimitive, ToPrimitive}; use num_traits::{FromPrimitive, ToPrimitive};
@ -21,6 +22,7 @@ use libcortex_a9::sync_channel;
use libasync::{smoltcp::{Sockets, TcpStream}, task}; use libasync::{smoltcp::{Sockets, TcpStream}, task};
use crate::kernel; use crate::kernel;
use crate::control::KernelControl;
#[derive(Debug, Clone, Copy, PartialEq, Eq)] #[derive(Debug, Clone, Copy, PartialEq, Eq)]
@ -141,7 +143,7 @@ async fn send_header(stream: &TcpStream, reply: Reply) -> Result<()> {
Ok(()) Ok(())
} }
async fn handle_connection(stream: TcpStream) -> Result<()> { async fn handle_connection(stream: TcpStream, control: Rc<RefCell<Option<KernelControl>>>) -> Result<()> {
expect(&stream, b"ARTIQ coredev\n").await?; expect(&stream, b"ARTIQ coredev\n").await?;
loop { loop {
expect(&stream, &[0x5a, 0x5a, 0x5a, 0x5a]).await?; expect(&stream, &[0x5a, 0x5a, 0x5a, 0x5a]).await?;
@ -163,6 +165,14 @@ async fn handle_connection(stream: TcpStream) -> Result<()> {
send_header(&stream, Reply::LoadCompleted).await?; send_header(&stream, Reply::LoadCompleted).await?;
} }
println!("length={}, {:?}", length, &kernel_buffer[..256]); println!("length={}, {:?}", length, &kernel_buffer[..256]);
// TODO: dyld
control.borrow_mut()
.take()
.map(|control| control.reset());
*control.borrow_mut() = Some(KernelControl::start(8192));
} }
_ => return Err(Error::UnrecognizedPacket) _ => return Err(Error::UnrecognizedPacket)
} }
@ -173,7 +183,7 @@ async fn handle_connection(stream: TcpStream) -> Result<()> {
const HWADDR: [u8; 6] = [0, 0x23, 0xab, 0xad, 0x1d, 0xea]; const HWADDR: [u8; 6] = [0, 0x23, 0xab, 0xad, 0x1d, 0xea];
const IPADDR: IpAddress = IpAddress::Ipv4(Ipv4Address([192, 168, 1, 52])); const IPADDR: IpAddress = IpAddress::Ipv4(Ipv4Address([192, 168, 1, 52]));
pub fn main(mut sc_tx: sync_channel::Sender<usize>, mut sc_rx: sync_channel::Receiver<usize>) { pub fn main() {
let eth = zynq::eth::Eth::default(HWADDR.clone()); let eth = zynq::eth::Eth::default(HWADDR.clone());
const RX_LEN: usize = 8; const RX_LEN: usize = 8;
let mut rx_descs = (0..RX_LEN) let mut rx_descs = (0..RX_LEN)
@ -209,11 +219,14 @@ pub fn main(mut sc_tx: sync_channel::Sender<usize>, mut sc_rx: sync_channel::Rec
Sockets::init(32); Sockets::init(32);
task::spawn(async { let control: Rc<RefCell<Option<KernelControl>>> = Rc::new(RefCell::new(None));
task::spawn(async move {
loop { loop {
while let stream = TcpStream::accept(1381, 2048, 2048).await.unwrap() { while let stream = TcpStream::accept(1381, 2048, 2048).await.unwrap() {
let control = control.clone();
task::spawn(async { task::spawn(async {
let _ = handle_connection(stream) let _ = handle_connection(stream, control)
.await .await
.map_err(|e| println!("Connection: {}", e)); .map_err(|e| println!("Connection: {}", e));
}); });

38
runtime/src/control.rs Normal file
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@ -0,0 +1,38 @@
use alloc::{vec, vec::Vec};
use libcortex_a9::{mutex::Mutex, sync_channel::{self, sync_channel}};
use libsupport_zynq::boot::Core1;
pub static CHANNEL_0TO1: Mutex<Option<sync_channel::Receiver<usize>>> = Mutex::new(None);
pub static CHANNEL_1TO0: Mutex<Option<sync_channel::Sender<usize>>> = Mutex::new(None);
/// Interface for core 0 to control core 1 start and reset
pub struct KernelControl {
core1: Core1<Vec<u32>>,
pub tx: sync_channel::Sender<usize>,
pub rx: sync_channel::Receiver<usize>,
}
impl KernelControl {
pub fn start(stack_size: usize) -> Self {
let stack = vec![0; stack_size / 4];
let core1 = Core1::start(stack);
let (core0_tx, core1_rx) = sync_channel(4);
let (core1_tx, core0_rx) = sync_channel(4);
*CHANNEL_0TO1.lock() = Some(core1_rx);
*CHANNEL_1TO0.lock() = Some(core1_tx);
KernelControl {
core1,
tx: core0_tx,
rx: core0_rx,
}
}
pub fn reset(self) {
*CHANNEL_0TO1.lock() = None;
*CHANNEL_1TO0.lock() = None;
self.core1.reset();
}
}

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@ -16,6 +16,7 @@ mod comms;
mod pl; mod pl;
mod rtio; mod rtio;
mod kernel; mod kernel;
mod control;
fn identifier_read(buf: &mut [u8]) -> &str { fn identifier_read(buf: &mut [u8]) -> &str {
@ -50,15 +51,7 @@ pub fn main_core0() {
println!("Detected gateware: {}", identifier_read(&mut [0; 64])); println!("Detected gateware: {}", identifier_read(&mut [0; 64]));
let core1_stack = unsafe { &mut STACK_CORE1[..] }; comms::main();
let core1 = boot::Core1::start(core1_stack);
let (mut core0_tx, core1_rx) = sync_channel(4);
let (core1_tx, mut core0_rx) = sync_channel(4);
*CHANNEL_0TO1.lock() = Some(core1_rx);
*CHANNEL_1TO0.lock() = Some(core1_tx);
comms::main(core0_tx, core0_rx);
} }
#[no_mangle] #[no_mangle]