forked from M-Labs/nac3
96 lines
2.0 KiB
INI
96 lines
2.0 KiB
INI
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#
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# Xilinx Zynq 7000 SoC
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#
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# Chris Johns <chrisj@rtems.org>
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#
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# Setup
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# -----
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#
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# Create a user configuration following the "Configuration Basics" in the user
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# documentation. In the file have:
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#
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# source [find interface/ftdi/flyswatter2.cfg]
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# source [find board/zynq-zc706-eval.cfg]
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# adapter_khz 2000
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# init
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#
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if { [info exists CHIPNAME] } {
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global _CHIPNAME
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set _CHIPNAME $CHIPNAME
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} else {
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global _CHIPNAME
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set _CHIPNAME zynq
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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# this defaults to a bigendian
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set _ENDIAN little
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}
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if { [info exists SMP] } {
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global _SMP
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set _SMP 1
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} else {
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global _SMP
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set _SMP 0
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}
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#
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# PL Tap.
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#
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# See ug585 ZYNQ-7000 TRM PSS_IDCODE for how this number is constructed.
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# 0x03731093 - ZC706 Eval board 1.1
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# 0x23731093 - ??
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# 0x23727093 - Zedboard Rev. C and D
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#
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# Set in your configuration file or board specific file.
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#
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if { [info exists PL_TAPID] } {
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set _PL_TAPID $PL_TAPID
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} else {
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set _PL_TAPID 0x03731093
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}
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jtag newtap $_CHIPNAME tap -irlen 6 -ircapture 0x001 -irmask 0x003 \
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-expected-id $_PL_TAPID
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#
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# CoreSight Debug Access Port
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#
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if { [info exists DAP_TAPID] } {
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set _DAP_TAPID $DAP_TAPID
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} else {
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set _DAP_TAPID 0x4ba00477
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}
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jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x03 \
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-expected-id $_DAP_TAPID
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#
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# GDB target: Cortex-A9, using DAP, configuring only one core
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# Base addresses of cores:
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# core 0 - 0xF8890000
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# core 1 - 0xF8892000
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#
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# Read from the ROM table with the patch to read the nested table.
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#
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set _TARGETNAME_0 $_CHIPNAME.cpu.0
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set _TARGETNAME_1 $_CHIPNAME.cpu.1
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target create $_TARGETNAME_0 cortex_a -coreid 0 \
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-endian $_ENDIAN \
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-chain-position $_CHIPNAME.dap \
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-dbgbase 0x80090000
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if { $_SMP } {
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echo "Zynq CPU1."
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target create $_TARGETNAME_1 cortex_a -coreid 1 \
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-endian $_ENDIAN \
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-chain-position $_CHIPNAME.dap \
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-dbgbase 0x80092000
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target smp $_TARGETNAME_0 $_TARGETNAME_1
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}
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