forked from M-Labs/artiq-zynq
add ACP kernel initiator
Based on work by Chris Ballance https://github.com/m-labs/artiq/issues/1167#issuecomment-427188287 M-Labs/artiq-zynq#55 Work-in-progress, only gateware part and build system, untested.
This commit is contained in:
parent
c9bac028bf
commit
f8d4036451
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@ -9,7 +9,11 @@ all: ../build/firmware/armv7-none-eabihf/release/szl
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mkdir -p ../build
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python gateware/zc706.py -r ../build/pl.rs -V $(VARIANT)
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../build/firmware/armv7-none-eabihf/release/runtime: ../build/pl.rs $(shell find . -path ./szl -prune -o -print)
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../build/rustc-cfg: gateware/*
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mkdir -p ../build
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python gateware/zc706.py -c ../build/rustc-cfg -V $(VARIANT)
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../build/firmware/armv7-none-eabihf/release/runtime: ../build/pl.rs ../build/rustc-cfg $(shell find . -path ./szl -prune -o -print)
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XBUILD_SYSROOT_PATH=`pwd`/../build/sysroot cargo xbuild --release -p runtime --target-dir ../build/firmware
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../build/szl-payload.bin.lzma: ../build/firmware/armv7-none-eabihf/release/runtime
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@ -0,0 +1,260 @@
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from operator import attrgetter
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from migen import *
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from migen.genlib.cdc import MultiReg
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from migen_axi.interconnect import axi
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from misoc.interconnect.csr import *
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from artiq.gateware import rtio
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OUT_BURST_LEN = 4
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IN_BURST_LEN = 4
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class Engine(Module, AutoCSR):
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def __init__(self, bus, user):
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self.addr_base = CSRStorage(32)
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self.trig_count = CSRStatus(32)
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self.write_count = CSRStatus(32)
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self.trigger_stb = Signal()
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# Dout : Data received from CPU, output by DMA module
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# Din : Data driven into DMA module, written into CPU
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# When stb assert, index shows word being read/written, dout/din holds
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# data
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#
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# Cycle:
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# trigger_stb pulsed at start
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# Then out_burst_len words are strobed out of dout
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# Then, when din_ready is high, in_burst_len words are strobed in to din
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self.dout_stb = Signal()
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self.din_stb = Signal()
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self.dout_index = Signal(max=16)
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self.din_index = Signal(max=16)
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self.din_ready = Signal()
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self.dout = Signal(64)
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self.din = Signal(64)
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###
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self.sync += If(self.trigger_stb, self.trig_count.status.eq(self.trig_count.status+1))
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self.comb += [
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user.aruser.eq(0x1f),
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user.awuser.eq(0x1f)
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]
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ar, aw, w, r, b = attrgetter("ar", "aw", "w", "r", "b")(bus)
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### Read
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self.comb += [
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ar.addr.eq(self.addr_base.storage),
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self.dout.eq(r.data),
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r.ready.eq(1),
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ar.burst.eq(axi.Burst.incr.value),
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ar.len.eq(OUT_BURST_LEN-1), # Number of transfers in burst (0->1 transfer, 1->2 transfers...)
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ar.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits
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ar.cache.eq(0xf),
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]
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# read control
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self.submodules.read_fsm = read_fsm = FSM(reset_state="IDLE")
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read_fsm.act("IDLE",
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If(self.trigger_stb,
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ar.valid.eq(1),
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If(ar.ready,
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NextState("READ")
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).Else(
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NextState("READ_START")
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)
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)
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)
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read_fsm.act("READ_START",
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ar.valid.eq(1),
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If(ar.ready,
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NextState("READ"),
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)
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)
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read_fsm.act("READ",
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ar.valid.eq(0),
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If(r.last & r.valid,
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NextState("IDLE")
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)
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)
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self.sync += [
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If(read_fsm.ongoing("IDLE"),
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self.dout_index.eq(0)
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).Else(If(r.valid & read_fsm.ongoing("READ"),
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self.dout_index.eq(self.dout_index+1)
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)
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)
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]
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self.comb += self.dout_stb.eq(r.valid & r.ready)
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### Write
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self.comb += [
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w.data.eq(self.din),
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aw.addr.eq(self.addr_base.storage+32), # Write to next cache line
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w.strb.eq(0xff),
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aw.burst.eq(axi.Burst.incr.value),
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aw.len.eq(IN_BURST_LEN-1), # Number of transfers in burst minus 1
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aw.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits
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aw.cache.eq(0xf),
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b.ready.eq(1),
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]
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# write control
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self.submodules.write_fsm = write_fsm = FSM(reset_state="IDLE")
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write_fsm.act("IDLE",
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w.valid.eq(0),
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aw.valid.eq(0),
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If(self.trigger_stb,
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aw.valid.eq(1),
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If(aw.ready, # assumes aw.ready is not randomly deasserted
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NextState("DATA_WAIT")
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).Else(
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NextState("AW_READY_WAIT")
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)
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)
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)
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write_fsm.act("AW_READY_WAIT",
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aw.valid.eq(1),
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If(aw.ready,
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NextState("DATA_WAIT"),
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)
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)
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write_fsm.act("DATA_WAIT",
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aw.valid.eq(0),
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If(self.din_ready,
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w.valid.eq(1),
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NextState("WRITE")
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)
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)
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write_fsm.act("WRITE",
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w.valid.eq(1),
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If(w.ready & w.last,
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NextState("IDLE")
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)
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)
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self.sync += If(w.ready & w.valid, self.write_count.status.eq(self.write_count.status+1))
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self.sync += [
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If(write_fsm.ongoing("IDLE"),
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self.din_index.eq(0)
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),
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If(w.ready & w.valid, self.din_index.eq(self.din_index+1))
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]
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self.comb += [
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w.last.eq(0),
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If(self.din_index==aw.len, w.last.eq(1))
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]
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self.comb += self.din_stb.eq(w.valid & w.ready)
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class KernelInitiator(Module, AutoCSR):
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def __init__(self, tsc, bus, user, evento):
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# Core is disabled upon reset to avoid spurious triggering if evento toggles from e.g. boot code.
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self.enable = CSRStorage()
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self.counter = CSRStatus(64)
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self.counter_update = CSR()
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self.submodules.engine = Engine(bus, user)
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self.cri = rtio.cri.Interface()
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###
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evento_stb = Signal()
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evento_latched = Signal()
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evento_latched_d = Signal()
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self.specials += MultiReg(evento, evento_latched)
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self.sync += evento_latched_d.eq(evento_latched)
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self.comb += self.engine.trigger_stb.eq(self.enable.storage & (evento_latched != evento_latched_d))
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cri = self.cri
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cmd = Signal(8)
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cmd_write = Signal()
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cmd_read = Signal()
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self.comb += [
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cmd_write.eq(cmd == 0),
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cmd_read.eq(cmd == 1)
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]
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dout_cases = {}
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dout_lw = Signal(32)
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dout_hw = Signal(32)
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self.comb += [
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dout_lw.eq(self.engine.dout[:32]),
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dout_hw.eq(self.engine.dout[32:])
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]
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dout_cases[0] = [
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cmd.eq(dout_lw[24:]),
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cri.chan_sel.eq(dout_lw[:24]),
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cri.o_address.eq(dout_hw[:16])
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]
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dout_cases[1] = [
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cri.o_timestamp.eq(self.engine.dout)
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]
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dout_cases[2] = [cri.o_data.eq(self.engine.dout)] # only lowest 64 bits
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self.sync += [
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cri.cmd.eq(rtio.cri.commands["nop"]),
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If(self.engine.dout_stb,
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Case(self.engine.dout_index, dout_cases),
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If(self.engine.dout_index == 2,
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If(cmd_write, cri.cmd.eq(rtio.cri.commands["write"])),
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If(cmd_read, cri.cmd.eq(rtio.cri.commands["read"]))
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)
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)
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]
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# If input event, wait for response before allow input data to be
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# sampled
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# TODO: If output, wait for wait flag clear
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RTIO_I_STATUS_WAIT_STATUS = 4
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RTIO_O_STATUS_WAIT = 1
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(self.engine.trigger_stb, NextState("WAIT_OUT_CYCLE"))
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)
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fsm.act("WAIT_OUT_CYCLE",
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self.engine.din_ready.eq(0),
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If(self.engine.dout_stb & (self.engine.dout_index == 3),
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NextState("WAIT_READY")
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)
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)
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fsm.act("WAIT_READY",
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If(cmd_read & (cri.i_status & RTIO_I_STATUS_WAIT_STATUS == 0) \
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| cmd_write & ~(cri.o_status & RTIO_O_STATUS_WAIT),
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self.engine.din_ready.eq(1),
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NextState("IDLE")
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)
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)
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din_cases_cmdwrite = {
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0: [self.engine.din.eq((1<<16) | cri.o_status)],
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1: [self.engine.din.eq(0)],
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}
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din_cases_cmdread = {
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0: [self.engine.din[:32].eq((1<<16) | cri.i_status), self.engine.din[32:].eq(cri.i_data)],
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1: [self.engine.din.eq(cri.i_timestamp)]
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}
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self.comb += [
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If(cmd_read, Case(self.engine.din_index, din_cases_cmdread)),
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If(cmd_write, Case(self.engine.din_index, din_cases_cmdwrite)),
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]
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# RTIO counter access
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self.sync += If(self.counter_update.re, self.counter.status.eq(tsc.full_ts_cri))
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@ -1,6 +1,7 @@
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#!/usr/bin/env python
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import argparse
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from operator import itemgetter
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from migen import *
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from migen.build.generic_platform import *
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@ -16,6 +17,7 @@ from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
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import dma
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import analyzer
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import acpki
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class RTIOCRG(Module, AutoCSR):
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@ -63,12 +65,18 @@ class RTIOCRG(Module, AutoCSR):
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class ZC706(SoCCore):
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def __init__(self):
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def __init__(self, acpki=False):
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self.acpki = acpki
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self.rustc_cfg = dict()
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platform = zc706.Platform()
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platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=self.__class__.__name__)
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ident = self.__class__.__name__
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if self.acpki:
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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@ -84,9 +92,20 @@ class ZC706(SoCCore):
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
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if self.acpki:
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self.rustc_cfg["ki_impl"] = "csr"
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
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self.csr_devices.append("rtio")
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else:
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self.rustc_cfg["ki_impl"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
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self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
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self.csr_devices.append("rtio")
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self.csr_devices.append("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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@ -103,8 +122,8 @@ class ZC706(SoCCore):
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class Simple(ZC706):
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def __init__(self):
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ZC706.__init__(self)
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def __init__(self, **kwargs):
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ZC706.__init__(self, **kwargs)
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platform = self.platform
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@ -134,8 +153,8 @@ class NIST_CLOCK(ZC706):
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"""
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NIST clock hardware, with old backplane and 11 DDS channels
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"""
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def __init__(self):
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ZC706.__init__(self)
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def __init__(self, **kwargs):
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ZC706.__init__(self, **kwargs)
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platform = self.platform
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platform.add_extension(nist_clock.fmc_adapter_io)
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@ -188,8 +207,8 @@ class NIST_QC2(ZC706):
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NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
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and 24 DDS channels. Two backplanes are used.
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"""
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def __init__(self):
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ZC706.__init__(self)
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def __init__(self, **kwargs):
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ZC706.__init__(self, **kwargs)
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platform = self.platform
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platform.add_extension(nist_qc2.fmc_adapter_io)
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@ -242,31 +261,48 @@ def write_csr_file(soc, filename):
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soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
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def write_rustc_cfg_file(soc, filename):
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with open(filename, "w") as f:
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for k, v in sorted(soc.rustc_cfg.items(), key=itemgetter(0)):
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if v is None:
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f.write("{}\n".format(k))
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else:
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f.write("{}=\"{}\"\n".format(k, v))
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ port to the ZC706 Zynq development kit")
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parser.add_argument("-r", default=None,
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help="build Rust interface into the specified file")
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parser.add_argument("-c", default=None,
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help="build Rust compiler configuration into the specified file")
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parser.add_argument("-g", default=None,
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help="build gateware into the specified directory")
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parser.add_argument("-V", "--variant", default="simple",
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help="variant: "
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"simple/nist_clock/nist_qc2 "
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"[acpki_]simple/nist_clock/nist_qc2 "
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"(default: %(default)s)")
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args = parser.parse_args()
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variant = args.variant.lower()
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acpki = variant.startswith("acpki_")
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if acpki:
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variant = variant[6:]
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try:
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cls = VARIANTS[args.variant.lower()]
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cls = VARIANTS[variant]
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except KeyError:
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raise SystemExit("Invalid variant (-V/--variant)")
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soc = cls()
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soc = cls(acpki=acpki)
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soc.finalize()
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if args.g is not None:
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soc.build(build_dir=args.g)
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if args.r is not None:
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write_csr_file(soc, args.r)
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if args.c is not None:
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write_rustc_cfg_file(soc, args.c)
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if args.g is not None:
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soc.build(build_dir=args.g)
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if __name__ == "__main__":
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|
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@ -1,6 +1,7 @@
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use std::env;
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use std::fs::File;
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use std::io::Write;
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use std::io::{BufRead, BufReader};
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use std::path::PathBuf;
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||||
fn main() {
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@ -15,4 +16,13 @@ fn main() {
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// Only re-run the build script when link.x is changed,
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// instead of when any part of the source code changes.
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println!("cargo:rerun-if-changed=link.x");
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// Handle rustc-cfg file
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let cfg_path = "../../build/rustc-cfg";
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println!("cargo:rerun-if-changed={}", cfg_path);
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let f = BufReader::new(File::open(cfg_path).unwrap());
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for line in f.lines() {
|
||||
println!("cargo:rustc-cfg={}", line.unwrap());
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -31,6 +31,11 @@ mod comms;
|
|||
mod rpc;
|
||||
#[path = "../../../build/pl.rs"]
|
||||
mod pl;
|
||||
#[cfg(ki_impl = "csr")]
|
||||
#[path = "rtio_csr.rs"]
|
||||
mod rtio;
|
||||
#[cfg(ki_impl = "acp")]
|
||||
#[path = "rtio_acp.rs"]
|
||||
mod rtio;
|
||||
mod kernel;
|
||||
mod moninj;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,81 @@
|
|||
use core::ptr::{self, read_volatile, write_volatile};
|
||||
use core::ffi::VaList;
|
||||
use alloc::vec;
|
||||
use cslice::CSlice;
|
||||
use libc::{c_char, c_int, size_t};
|
||||
|
||||
use crate::artiq_raise;
|
||||
|
||||
use crate::pl::csr;
|
||||
|
||||
|
||||
#[repr(C)]
|
||||
pub struct TimestampedData {
|
||||
timestamp: i64,
|
||||
data: i32,
|
||||
}
|
||||
|
||||
pub extern fn init() {
|
||||
unsafe {
|
||||
csr::rtio_core::reset_write(1);
|
||||
}
|
||||
}
|
||||
|
||||
pub extern fn get_destination_status(destination: i32) -> bool {
|
||||
// TODO
|
||||
destination == 0
|
||||
}
|
||||
|
||||
pub extern fn get_counter() -> i64 {
|
||||
unsafe {
|
||||
csr::rtio::counter_update_write(1);
|
||||
csr::rtio::counter_read() as i64
|
||||
}
|
||||
}
|
||||
|
||||
pub extern fn now_mu() -> i64 {
|
||||
unimplemented!();
|
||||
}
|
||||
|
||||
pub extern fn at_mu(t: i64) {
|
||||
unimplemented!();
|
||||
}
|
||||
|
||||
pub extern fn delay_mu(dt: i64) {
|
||||
unimplemented!();
|
||||
}
|
||||
|
||||
pub extern fn output(target: i32, data: i32) {
|
||||
unimplemented!();
|
||||
}
|
||||
|
||||
pub extern fn output_wide(target: i32, data: CSlice<i32>) {
|
||||
unimplemented!();
|
||||
}
|
||||
|
||||
pub extern fn input_timestamp(timeout: i64, channel: i32) -> i64 {
|
||||
unimplemented!();
|
||||
}
|
||||
|
||||
pub extern fn input_data(channel: i32) -> i32 {
|
||||
unimplemented!();
|
||||
}
|
||||
|
||||
pub extern fn input_timestamped_data(timeout: i64, channel: i32) -> TimestampedData {
|
||||
unimplemented!();
|
||||
}
|
||||
|
||||
extern "C" {
|
||||
fn vsnprintf_(buffer: *mut c_char, count: size_t, format: *const c_char, va: VaList) -> c_int;
|
||||
}
|
||||
|
||||
fn write_rtio_log(data: &[i8]) {
|
||||
unimplemented!();
|
||||
}
|
||||
|
||||
pub unsafe extern fn log(fmt: *const c_char, mut args: ...) {
|
||||
let size = vsnprintf_(ptr::null_mut(), 0, fmt, args.as_va_list()) as usize;
|
||||
let mut buf = vec![0; size + 1];
|
||||
vsnprintf_(buf.as_mut_ptr(), size + 1, fmt, args.as_va_list());
|
||||
write_rtio_log(buf.as_slice());
|
||||
}
|
||||
Loading…
Reference in New Issue