forked from M-Labs/artiq-zynq
zynq_clocking: Allow ext signal to set cur_clk csr
- for example, current_clock csr can be connected to tx_init.done
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07044752b6
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e6372b9766
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@ -65,7 +65,7 @@ class ClockSwitchFSM(Module):
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class SYSCRG(Module, AutoCSR):
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def __init__(self, platform, ps7, main_clk, clk_sw=None, freq=125e6, ext_async_rst=None):
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def __init__(self, platform, ps7, main_clk, clk_sw=None, clk_sw_status=None, freq=125e6, ext_async_rst=None, ):
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# assumes bootstrap clock is same freq as main and sys output
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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@ -148,4 +148,7 @@ class SYSCRG(Module, AutoCSR):
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)
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self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
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self.comb += self.current_clock.status.eq(self.clk_sw_fsm.o_clk_sw)
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if clk_sw_status is None:
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self.comb += self.current_clock.status.eq(self.clk_sw_fsm.o_clk_sw)
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else:
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self.comb += self.current_clock.status.eq(clk_sw_status)
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