forked from M-Labs/artiq-zynq
satman: wait longer for PLL lock (#246)
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@ -633,7 +633,7 @@ pub extern "C" fn main_core0() -> i32 {
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unsafe {
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csr::drtio_transceiver::stable_clkin_write(1);
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}
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timer.delay_us(20_000); // wait for CPLL/QPLL/MMCM lock
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timer.delay_us(50_000); // wait for CPLL/QPLL/MMCM lock
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let clk = unsafe { csr::sys_crg::current_clock_read() };
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if clk == 1 {
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info!("SYS CLK switched successfully");
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