forked from M-Labs/artiq-zynq
kernel: flush now write-buffered dcache of image before execution
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06ad8dfe27
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@ -23,7 +23,7 @@ pub struct DynamicSection {
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/// target memory image
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/// target memory image
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pub struct Image {
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pub struct Image {
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layout: Layout,
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layout: Layout,
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data: &'static mut [u8],
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pub data: &'static mut [u8],
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}
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}
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impl Image {
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impl Image {
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@ -58,7 +58,7 @@ fn elf_hash(name: &[u8]) -> u32 {
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}
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}
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pub struct Library {
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pub struct Library {
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image: Image,
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pub image: Image,
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dyn_section: DynamicSection,
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dyn_section: DynamicSection,
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}
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}
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@ -3,7 +3,7 @@ use log::{debug, error};
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use alloc::{vec::Vec, sync::Arc};
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use alloc::{vec::Vec, sync::Arc};
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use cslice::CSlice;
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use cslice::CSlice;
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use libcortex_a9::{mutex::Mutex, sync_channel::{self, sync_channel}};
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use libcortex_a9::{cache::dcci_slice, mutex::Mutex, sync_channel::{self, sync_channel}};
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use libsupport_zynq::boot::Core1;
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use libsupport_zynq::boot::Core1;
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use dyld;
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use dyld;
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@ -313,6 +313,10 @@ pub fn main_core1() {
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current_modinit = Some(__modinit__);
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current_modinit = Some(__modinit__);
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current_typeinfo = library.lookup(b"typeinfo");
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current_typeinfo = library.lookup(b"typeinfo");
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debug!("kernel loaded");
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debug!("kernel loaded");
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// Flush data cache entries for the image in DDR, including
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// Memory/Instruction Symchronization Barriers
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dcci_slice(library.image.data);
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core1_tx.send(Message::LoadCompleted);
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core1_tx.send(Message::LoadCompleted);
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},
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},
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Err(error) => {
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Err(error) => {
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