abdul124
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Pull Requests Activity

fix analyzer target for masters

This commit is contained in:
spaqin 2023-05-22 15:32:49 +08:00
parent 6b9212525a
commit d51f86672a
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/gateware/kasli_soc.py
View File

@ -311,7 +311,7 @@ class GenericMaster(SoCCore):
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con) self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table") self.csr_devices.append("routing_table")
self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri, self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.cri_con.switch.slave,
self.ps7.s_axi_hp1) self.ps7.s_axi_hp1)
self.csr_devices.append("rtio_analyzer") self.csr_devices.append("rtio_analyzer")

2
src/gateware/zc706.py
View File

@ -320,7 +320,7 @@ class _MasterBase(SoCCore):
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj") self.csr_devices.append("rtio_moninj")
self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri, self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.cri_con.switch.slave,
self.ps7.s_axi_hp1) self.ps7.s_axi_hp1)
self.csr_devices.append("rtio_analyzer") self.csr_devices.append("rtio_analyzer")