forked from M-Labs/artiq-zynq
fix analyzer target for masters
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6b9212525a
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@ -311,7 +311,7 @@ class GenericMaster(SoCCore):
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self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
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self.csr_devices.append("routing_table")
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self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
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self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.cri_con.switch.slave,
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self.ps7.s_axi_hp1)
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self.csr_devices.append("rtio_analyzer")
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@ -320,7 +320,7 @@ class _MasterBase(SoCCore):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
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self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.cri_con.switch.slave,
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self.ps7.s_axi_hp1)
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self.csr_devices.append("rtio_analyzer")
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