forked from M-Labs/artiq-zynq
Firmware: Satman skew calibration & tester
cargo template: add calibrate_wrpll_skew feature tag collector: add TAG_OFFSET for Satman WRPLL tag collector: add TAG_OFFSET getter & setter for calibration wrpll: add skew tester and calibration wrpll: gate calibration behind calibrate_wrpll_skew feature
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@ -10,6 +10,7 @@ name = "libboard_artiq"
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[features]
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target_zc706 = ["libboard_zynq/target_zc706", "libconfig/target_zc706"]
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target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libconfig/target_kasli_soc"]
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calibrate_wrpll_skew = []
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[build-dependencies]
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build_zynq = { path = "../libbuild_zynq" }
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@ -355,6 +355,10 @@ pub mod wrpll {
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mod tag_collector {
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use super::*;
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#[cfg(wrpll_ref_clk = "GT_CDR")]
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static mut TAG_OFFSET: u32 = 19050;
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#[cfg(wrpll_ref_clk = "SMA_CLKIN")]
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static mut TAG_OFFSET: u32 = 0;
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static mut REF_TAG: u32 = 0;
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static mut REF_TAG_READY: bool = false;
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static mut MAIN_TAG: u32 = 0;
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@ -392,6 +396,18 @@ pub mod wrpll {
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unsafe { REF_TAG_READY && MAIN_TAG_READY }
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}
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#[cfg(feature = "calibrate_wrpll_skew")]
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pub fn set_tag_offset(offset: u32) {
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unsafe {
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TAG_OFFSET = offset;
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}
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}
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#[cfg(feature = "calibrate_wrpll_skew")]
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pub fn get_tag_offset() -> u32 {
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unsafe { TAG_OFFSET }
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}
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pub fn get_period_error() -> i32 {
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// n * BEATING_PERIOD - REF_TAG(n) mod BEATING_PERIOD
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let mut period_error = unsafe { REF_TAG.overflowing_neg().0.rem_euclid(BEATING_PERIOD as u32) as i32 };
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@ -403,9 +419,13 @@ pub mod wrpll {
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}
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pub fn get_phase_error() -> i32 {
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// MAIN_TAG(n) - REF_TAG(n) mod BEATING_PERIOD
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let mut phase_error =
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unsafe { MAIN_TAG.overflowing_sub(REF_TAG).0.rem_euclid(BEATING_PERIOD as u32) as i32 };
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// MAIN_TAG(n) - REF_TAG(n) - TAG_OFFSET mod BEATING_PERIOD
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let mut phase_error = unsafe {
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MAIN_TAG
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.overflowing_sub(REF_TAG + TAG_OFFSET)
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.0
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.rem_euclid(BEATING_PERIOD as u32) as i32
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};
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// mapping tags from [0, 2π] -> [-π, π]
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if phase_error > BEATING_HALFPERIOD {
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@ -520,6 +540,113 @@ pub mod wrpll {
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Ok(())
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}
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#[cfg(wrpll_ref_clk = "GT_CDR")]
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fn test_skew(timer: &mut GlobalTimer) -> Result<(), &'static str> {
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// wait for PLL to stabilize
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timer.delay_us(20_000);
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info!("testing the skew of SYS CLK...");
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if has_timing_error(timer) {
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return Err("the skew cannot satisfy setup/hold time constraint of RX synchronizer");
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}
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info!("the skew of SYS CLK met the timing constraint");
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Ok(())
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}
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#[cfg(wrpll_ref_clk = "GT_CDR")]
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fn has_timing_error(timer: &mut GlobalTimer) -> bool {
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unsafe {
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csr::wrpll_skewtester::error_write(1);
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}
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timer.delay_us(5_000);
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unsafe { csr::wrpll_skewtester::error_read() == 1 }
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}
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#[cfg(feature = "calibrate_wrpll_skew")]
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fn find_edge(target: bool, timer: &mut GlobalTimer) -> Result<u32, &'static str> {
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const STEP: u32 = 8;
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const STABLE_THRESHOLD: u32 = 10;
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enum FSM {
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Init,
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WaitEdge,
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GotEdge,
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}
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let mut state: FSM = FSM::Init;
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let mut offset: u32 = tag_collector::get_tag_offset();
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let mut median_edge: u32 = 0;
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let mut stable_counter: u32 = 0;
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for _ in 0..(BEATING_PERIOD as u32 / STEP) as usize {
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tag_collector::set_tag_offset(offset);
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offset += STEP;
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// wait for PLL to stabilize
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timer.delay_us(20_000);
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let error = has_timing_error(timer);
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// A median edge deglitcher
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match state {
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FSM::Init => {
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if error != target {
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stable_counter += 1;
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} else {
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stable_counter = 0;
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}
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if stable_counter >= STABLE_THRESHOLD {
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state = FSM::WaitEdge;
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stable_counter = 0;
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}
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}
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FSM::WaitEdge => {
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if error == target {
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state = FSM::GotEdge;
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median_edge = offset;
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}
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}
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FSM::GotEdge => {
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if error != target {
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median_edge += STEP;
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stable_counter = 0;
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} else {
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stable_counter += 1;
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}
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if stable_counter >= STABLE_THRESHOLD {
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return Ok(median_edge);
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}
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}
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}
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}
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return Err("failed to find timing error edge");
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}
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#[cfg(feature = "calibrate_wrpll_skew")]
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fn calibrate_skew(timer: &mut GlobalTimer) -> Result<(), &'static str> {
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info!("calibrating skew to meet timing constraint...");
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// clear calibrated value
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tag_collector::set_tag_offset(0);
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let rising = find_edge(true, timer)? as i32;
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let falling = find_edge(false, timer)? as i32;
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let width = BEATING_PERIOD - (falling - rising);
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let result = falling + width / 2;
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tag_collector::set_tag_offset(result as u32);
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info!(
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"calibration successful, error zone: {} -> {}, width: {} ({}deg), middle of working region: {}",
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rising,
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falling,
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width,
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360 * width / BEATING_PERIOD,
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result,
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);
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Ok(())
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}
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pub fn select_recovered_clock(rc: bool, timer: &mut GlobalTimer) {
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set_isr(false);
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@ -537,6 +664,12 @@ pub mod wrpll {
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// use nFIQ to avoid IRQ being disabled by mutex lock and mess up PLL
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set_isr(true);
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info!("WRPLL interrupt enabled");
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#[cfg(feature = "calibrate_wrpll_skew")]
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calibrate_skew(timer).expect("failed to set the correct skew");
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#[cfg(wrpll_ref_clk = "GT_CDR")]
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test_skew(timer).expect("skew test failed");
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}
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}
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}
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@ -7,6 +7,7 @@ build = "build.rs"
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[features]
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target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706", "libboard_artiq/target_zc706"]
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target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc", "libconfig/target_kasli_soc", "libboard_artiq/target_kasli_soc"]
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calibrate_wrpll_skew = ["libboard_artiq/calibrate_wrpll_skew"]
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default = ["target_zc706", ]
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[build-dependencies]
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