forked from M-Labs/artiq-zynq
kasli_soc: Add support for shuttler on gateware
- Port from artiq repo - Add EEM_DRTIO gateware
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@ -16,7 +16,7 @@ from artiq.coredevice import jsondesc
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from artiq.gateware import rtio, eem_7series
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from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
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from artiq.gateware.rtio.phy import ttl_simple
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from artiq.gateware.drtio.transceiver import gtx_7series
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from artiq.gateware.drtio.transceiver import gtx_7series, eem_serdes
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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@ -201,6 +201,7 @@ class GenericMaster(SoCCore):
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def __init__(self, description, acpki=False):
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clk_freq = description["rtio_frequency"]
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has_drtio_over_eem = any(peripheral["type"] == "shuttler" for peripheral in description["peripherals"])
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self.acpki = acpki
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platform = kasli_soc.Platform()
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@ -246,6 +247,8 @@ class GenericMaster(SoCCore):
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self.rtio_channels = []
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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if has_drtio_over_eem:
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self.eem_drtio_channels = []
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if has_grabber:
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self.grabber_csr_group = []
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eem_7series.add_peripherals(self, description["peripherals"], iostandard=eem_iostandard)
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@ -260,17 +263,17 @@ class GenericMaster(SoCCore):
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self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
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drtio_csr_group = []
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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self.drtio_csr_group = []
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self.drtioaux_csr_group = []
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self.drtioaux_memory_group = []
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self.drtio_cri = []
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for i in range(len(self.gt_drtio.channels)):
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core_name = "drtio" + str(i)
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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drtio_csr_group.append(core_name)
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drtioaux_csr_group.append(coreaux_name)
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drtioaux_memory_group.append(memory_name)
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self.drtio_csr_group.append(core_name)
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self.drtioaux_csr_group.append(coreaux_name)
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self.drtioaux_memory_group.append(memory_name)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
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@ -289,9 +292,10 @@ class GenericMaster(SoCCore):
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self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2)
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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self.add_csr_group("drtio", drtio_csr_group)
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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if has_drtio_over_eem:
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self.add_eem_drtio(self.eem_drtio_channels)
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self.add_drtio_cpuif_groups()
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self.submodules.rtio_core = rtio.Core(
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self.rtio_tsc, self.rtio_channels, lane_count=description["sed_lanes"]
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@ -340,6 +344,42 @@ class GenericMaster(SoCCore):
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self.comb += [self.virtual_leds.get(i).eq(channel.rx_ready)
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for i, channel in enumerate(self.gt_drtio.channels)]
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def add_eem_drtio(self, eem_drtio_channels):
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# Must be called before invoking add_rtio() to construct the CRI
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# interconnect properly
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self.submodules.eem_transceiver = eem_serdes.EEMSerdes(self.platform, eem_drtio_channels)
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self.csr_devices.append("eem_transceiver")
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self.config["HAS_DRTIO_EEM"] = None
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self.config["EEM_DRTIO_COUNT"] = len(eem_drtio_channels)
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cdr = ClockDomainsRenamer({"rtio_rx": "sys"})
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for i in range(len(self.eem_transceiver.channels)):
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channel = i + len(self.gt_drtio.channels)
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core_name = "drtio" + str(channel)
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coreaux_name = "drtioaux" + str(channel)
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memory_name = "drtioaux" + str(channel) + "_mem"
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self.drtio_csr_group.append(core_name)
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self.drtioaux_csr_group.append(coreaux_name)
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self.drtioaux_memory_group.append(memory_name)
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core = cdr(DRTIOMaster(self.rtio_tsc, self.eem_transceiver.channels[i]))
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setattr(self.submodules, core_name, core)
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self.drtio_cri.append(core.cri)
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self.csr_devices.append(core_name)
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coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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size = coreaux.get_mem_size()
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memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), size)
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self.axi2csr.register_port(coreaux.get_rx_port(), size)
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self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2)
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def add_drtio_cpuif_groups(self):
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self.add_csr_group("drtio", self.drtio_csr_group)
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self.add_csr_group("drtioaux", self.drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", self.drtioaux_memory_group)
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class GenericSatellite(SoCCore):
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