integrate inter-CPU communication

Cargo.lock

@@ -43,7 +43,7 @@ version = "0.1.0"
 [[package]]
 name = "libasync"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#526cfe7577c189687ed1fdca512120dd1460bb80"
+source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b26327e474ef224c91f704b7f513a1495a981f87"
 dependencies = [
  "libcortex_a9",
  "pin-utils",
@@ -53,7 +53,7 @@ dependencies = [
 [[package]]
 name = "libboard_zynq"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#526cfe7577c189687ed1fdca512120dd1460bb80"
+source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b26327e474ef224c91f704b7f513a1495a981f87"
 dependencies = [
  "bit_field",
  "libcortex_a9",
@@ -65,7 +65,7 @@ dependencies = [
 [[package]]
 name = "libcortex_a9"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#526cfe7577c189687ed1fdca512120dd1460bb80"
+source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b26327e474ef224c91f704b7f513a1495a981f87"
 dependencies = [
  "bit_field",
  "libregister",
@@ -74,7 +74,7 @@ dependencies = [
 [[package]]
 name = "libregister"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#526cfe7577c189687ed1fdca512120dd1460bb80"
+source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b26327e474ef224c91f704b7f513a1495a981f87"
 dependencies = [
  "bit_field",
  "vcell",
@@ -84,7 +84,7 @@ dependencies = [
 [[package]]
 name = "libsupport_zynq"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#526cfe7577c189687ed1fdca512120dd1460bb80"
+source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b26327e474ef224c91f704b7f513a1495a981f87"
 dependencies = [
  "compiler_builtins",
  "libboard_zynq",
@@ -164,6 +164,7 @@ dependencies = [
  "dyld",
  "libasync",
  "libboard_zynq",
+ "libcortex_a9",
  "libsupport_zynq",
  "num-derive",
  "num-traits",

runtime/Cargo.toml

@@ -15,5 +15,6 @@ num-derive = "0.3"
 cslice = "0.3"
 libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
 libsupport_zynq = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
+libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
 libasync = { git = "https://git.m-labs.hk/M-Labs/zc706.git" }
 dyld = { path = "../libdyld" }

runtime/src/comms.rs

@@ -15,7 +15,7 @@ use libboard_zynq::{
     },
 };
 use libsupport_zynq::alloc::{vec, vec::Vec};
-
+use libcortex_a9::sync_channel;
 use libasync::smoltcp::{Sockets, TcpStream};
 
 
@@ -118,7 +118,7 @@ async fn handle_connection(stream: TcpStream) -> Result<()> {
 const HWADDR: [u8; 6] = [0, 0x23, 0xab, 0xad, 0x1d, 0xea];
 const IPADDR: IpAddress = IpAddress::Ipv4(Ipv4Address([192, 168, 1, 52]));
 
-pub fn network_main() {
+pub fn main(mut sc_tx: sync_channel::Sender<usize>, mut sc_rx: sync_channel::Receiver<usize>) {
     let eth = zynq::eth::Eth::default(HWADDR.clone());
     const RX_LEN: usize = 8;
     let mut rx_descs = (0..RX_LEN)

runtime/src/kernel.rs

@@ -0,0 +1,9 @@
+use libcortex_a9::sync_channel;
+
+pub fn main(mut sc_tx: sync_channel::Sender<usize>, mut sc_rx: sync_channel::Receiver<usize>) {
+    for i in sc_rx {
+        sc_tx.send(*i * *i);
+    }
+
+	loop {}
+}

runtime/src/main.rs

@@ -9,12 +9,14 @@ use libboard_zynq::{
     println,
     self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll},
 };
-use libsupport_zynq::ram;
-
+use libsupport_zynq::{ram, boot};
+use libcortex_a9::{mutex::Mutex, sync_channel::{self, sync_channel}};
 
+mod comms;
 mod pl;
 mod rtio;
-mod network;
+mod kernel;
+
 
 fn identifier_read(buf: &mut [u8]) -> &str {
     unsafe {
@@ -29,6 +31,10 @@ fn identifier_read(buf: &mut [u8]) -> &str {
     }
 }
 
+static mut STACK_CORE1: [u32; 512] = [0; 512];
+static CHANNEL_0TO1: Mutex<Option<sync_channel::Receiver<usize>>> = Mutex::new(None);
+static CHANNEL_1TO0: Mutex<Option<sync_channel::Sender<usize>>> = Mutex::new(None);
+
 #[no_mangle]
 pub fn main_core0() {
     println!("ARTIQ runtime starting...");
@@ -44,11 +50,32 @@ pub fn main_core0() {
 
     println!("Detected gateware: {}", identifier_read(&mut [0; 64]));
 
-    network::network_main();
+    let core1_stack = unsafe { &mut STACK_CORE1[..] };
+    let core1 = boot::Core1::start(core1_stack);
+
+    let (mut core0_tx, core1_rx) = sync_channel(4);
+    let (core1_tx, mut core0_rx) = sync_channel(4);
+    *CHANNEL_0TO1.lock() = Some(core1_rx);
+    *CHANNEL_1TO0.lock() = Some(core1_tx);
+
+    comms::main(core0_tx, core0_rx);
 }
 
 #[no_mangle]
 pub fn main_core1() {
-    println!("[CORE1] hello world {}", identifier_read(&mut [0; 64]));
-    loop {}
+    println!("Core1 started");
+
+    let mut core1_tx = None;
+    while core1_tx.is_none() {
+        core1_tx = CHANNEL_1TO0.lock().take();
+    }
+    let mut core1_tx = core1_tx.unwrap();
+
+    let mut core1_rx = None;
+    while core1_rx.is_none() {
+        core1_rx = CHANNEL_0TO1.lock().take();
+    }
+    let mut core1_rx = core1_rx.unwrap();
+
+    kernel::main(core1_tx, core1_rx);
 }