forked from M-Labs/artiq-zynq
Revert "kasli-soc: work around I2C breakage (#130)"
This reverts commit f1fd55dee5
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This commit is contained in:
parent
cbcda286dc
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8128dc0b56
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@ -28,6 +28,15 @@ class RTIOCRG(Module, AutoCSR):
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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clk_synth = platform.request("cdr_clk_clean_fabric")
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clk_synth_se = Signal()
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platform.add_period_constraint(clk_synth.p, 8.0)
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self.specials += [
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Instance("IBUFGDS",
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
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i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se),
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]
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pll_locked = Signal()
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pll_locked = Signal()
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rtio_clk = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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rtiox4_clk = Signal()
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@ -38,7 +47,7 @@ class RTIOCRG(Module, AutoCSR):
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p_BANDWIDTH="HIGH",
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p_BANDWIDTH="HIGH",
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p_REF_JITTER1=0.001,
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p_REF_JITTER1=0.001,
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p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
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p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
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i_CLKIN2=ClockSignal(),
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i_CLKIN2=clk_synth_se,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=0,
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i_CLKINSEL=0,
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@ -199,9 +199,9 @@ pub fn main_core0() {
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info!("detected gateware: {}", identifier_read(&mut [0; 64]));
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info!("detected gateware: {}", identifier_read(&mut [0; 64]));
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i2c::init();
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i2c::init();
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/*#[cfg(feature = "target_kasli_soc")]
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#[cfg(feature = "target_kasli_soc")]
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si5324::setup(unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() },
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si5324::setup(unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() },
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&SI5324_SETTINGS, si5324::Input::Ckin1).expect("cannot initialize Si5324");*/
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&SI5324_SETTINGS, si5324::Input::Ckin1).expect("cannot initialize Si5324");
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let cfg = match Config::new() {
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let cfg = match Config::new() {
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Ok(cfg) => cfg,
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Ok(cfg) => cfg,
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