forked from M-Labs/artiq-zynq
merge control.rs into kernel.rs
This commit is contained in:
parent
105eb7c2bc
commit
6c18e24418
|
@ -18,11 +18,9 @@ use libboard_zynq::{
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
use libsupport_zynq::alloc::{vec, vec::Vec};
|
use libsupport_zynq::alloc::{vec, vec::Vec};
|
||||||
use libcortex_a9::sync_channel;
|
|
||||||
use libasync::{smoltcp::{Sockets, TcpStream}, task};
|
use libasync::{smoltcp::{Sockets, TcpStream}, task};
|
||||||
|
|
||||||
use crate::kernel;
|
use crate::kernel;
|
||||||
use crate::control::KernelControl;
|
|
||||||
|
|
||||||
|
|
||||||
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
|
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
|
||||||
|
@ -143,7 +141,7 @@ async fn send_header(stream: &TcpStream, reply: Reply) -> Result<()> {
|
||||||
Ok(())
|
Ok(())
|
||||||
}
|
}
|
||||||
|
|
||||||
async fn handle_connection(stream: TcpStream, control: Rc<RefCell<Option<KernelControl>>>) -> Result<()> {
|
async fn handle_connection(stream: TcpStream, control: Rc<RefCell<Option<kernel::Control>>>) -> Result<()> {
|
||||||
expect(&stream, b"ARTIQ coredev\n").await?;
|
expect(&stream, b"ARTIQ coredev\n").await?;
|
||||||
loop {
|
loop {
|
||||||
expect(&stream, &[0x5a, 0x5a, 0x5a, 0x5a]).await?;
|
expect(&stream, &[0x5a, 0x5a, 0x5a, 0x5a]).await?;
|
||||||
|
@ -172,7 +170,7 @@ async fn handle_connection(stream: TcpStream, control: Rc<RefCell<Option<KernelC
|
||||||
.take()
|
.take()
|
||||||
.map(|control| control.reset());
|
.map(|control| control.reset());
|
||||||
|
|
||||||
*control.borrow_mut() = Some(KernelControl::start(8192));
|
*control.borrow_mut() = Some(kernel::Control::start(8192));
|
||||||
}
|
}
|
||||||
_ => return Err(Error::UnrecognizedPacket)
|
_ => return Err(Error::UnrecognizedPacket)
|
||||||
}
|
}
|
||||||
|
@ -219,7 +217,7 @@ pub fn main() {
|
||||||
|
|
||||||
Sockets::init(32);
|
Sockets::init(32);
|
||||||
|
|
||||||
let control: Rc<RefCell<Option<KernelControl>>> = Rc::new(RefCell::new(None));
|
let control: Rc<RefCell<Option<kernel::Control>>> = Rc::new(RefCell::new(None));
|
||||||
|
|
||||||
task::spawn(async move {
|
task::spawn(async move {
|
||||||
loop {
|
loop {
|
||||||
|
|
|
@ -1,38 +0,0 @@
|
||||||
use alloc::{vec, vec::Vec};
|
|
||||||
use libcortex_a9::{mutex::Mutex, sync_channel::{self, sync_channel}};
|
|
||||||
use libsupport_zynq::boot::Core1;
|
|
||||||
|
|
||||||
pub static CHANNEL_0TO1: Mutex<Option<sync_channel::Receiver<usize>>> = Mutex::new(None);
|
|
||||||
pub static CHANNEL_1TO0: Mutex<Option<sync_channel::Sender<usize>>> = Mutex::new(None);
|
|
||||||
|
|
||||||
/// Interface for core 0 to control core 1 start and reset
|
|
||||||
pub struct KernelControl {
|
|
||||||
core1: Core1<Vec<u32>>,
|
|
||||||
pub tx: sync_channel::Sender<usize>,
|
|
||||||
pub rx: sync_channel::Receiver<usize>,
|
|
||||||
}
|
|
||||||
|
|
||||||
impl KernelControl {
|
|
||||||
pub fn start(stack_size: usize) -> Self {
|
|
||||||
let stack = vec![0; stack_size / 4];
|
|
||||||
let core1 = Core1::start(stack);
|
|
||||||
|
|
||||||
let (core0_tx, core1_rx) = sync_channel(4);
|
|
||||||
let (core1_tx, core0_rx) = sync_channel(4);
|
|
||||||
*CHANNEL_0TO1.lock() = Some(core1_rx);
|
|
||||||
*CHANNEL_1TO0.lock() = Some(core1_tx);
|
|
||||||
|
|
||||||
KernelControl {
|
|
||||||
core1,
|
|
||||||
tx: core0_tx,
|
|
||||||
rx: core0_rx,
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
pub fn reset(self) {
|
|
||||||
*CHANNEL_0TO1.lock() = None;
|
|
||||||
*CHANNEL_1TO0.lock() = None;
|
|
||||||
|
|
||||||
self.core1.reset();
|
|
||||||
}
|
|
||||||
}
|
|
|
@ -1,11 +1,63 @@
|
||||||
use libcortex_a9::sync_channel;
|
use alloc::{vec, vec::Vec};
|
||||||
|
use libcortex_a9::{mutex::Mutex, sync_channel::{self, sync_channel}};
|
||||||
|
use libboard_zynq::println;
|
||||||
|
use libsupport_zynq::boot::Core1;
|
||||||
|
|
||||||
|
static CHANNEL_0TO1: Mutex<Option<sync_channel::Receiver<usize>>> = Mutex::new(None);
|
||||||
|
static CHANNEL_1TO0: Mutex<Option<sync_channel::Sender<usize>>> = Mutex::new(None);
|
||||||
|
|
||||||
|
pub struct Control {
|
||||||
|
core1: Core1<Vec<u32>>,
|
||||||
|
pub tx: sync_channel::Sender<usize>,
|
||||||
|
pub rx: sync_channel::Receiver<usize>,
|
||||||
|
}
|
||||||
|
|
||||||
|
impl Control {
|
||||||
|
pub fn start(stack_size: usize) -> Self {
|
||||||
|
let stack = vec![0; stack_size / 4];
|
||||||
|
let core1 = Core1::start(stack);
|
||||||
|
|
||||||
|
let (core0_tx, core1_rx) = sync_channel(4);
|
||||||
|
let (core1_tx, core0_rx) = sync_channel(4);
|
||||||
|
*CHANNEL_0TO1.lock() = Some(core1_rx);
|
||||||
|
*CHANNEL_1TO0.lock() = Some(core1_tx);
|
||||||
|
|
||||||
|
Control {
|
||||||
|
core1,
|
||||||
|
tx: core0_tx,
|
||||||
|
rx: core0_rx,
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pub fn reset(self) {
|
||||||
|
*CHANNEL_0TO1.lock() = None;
|
||||||
|
*CHANNEL_1TO0.lock() = None;
|
||||||
|
|
||||||
|
self.core1.reset();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
pub static mut KERNEL_BUFFER: [u8; 16384] = [0; 16384];
|
pub static mut KERNEL_BUFFER: [u8; 16384] = [0; 16384];
|
||||||
|
|
||||||
pub fn main(mut sc_tx: sync_channel::Sender<usize>, mut sc_rx: sync_channel::Receiver<usize>) {
|
#[no_mangle]
|
||||||
for i in sc_rx {
|
pub fn main_core1() {
|
||||||
sc_tx.send(*i * *i);
|
println!("Core1 started");
|
||||||
|
|
||||||
|
let mut core1_tx = None;
|
||||||
|
while core1_tx.is_none() {
|
||||||
|
core1_tx = CHANNEL_1TO0.lock().take();
|
||||||
|
}
|
||||||
|
let mut core1_tx = core1_tx.unwrap();
|
||||||
|
|
||||||
|
let mut core1_rx = None;
|
||||||
|
while core1_rx.is_none() {
|
||||||
|
core1_rx = CHANNEL_0TO1.lock().take();
|
||||||
|
}
|
||||||
|
let core1_rx = core1_rx.unwrap();
|
||||||
|
|
||||||
|
for i in core1_rx {
|
||||||
|
core1_tx.send(*i * *i);
|
||||||
}
|
}
|
||||||
|
|
||||||
loop {}
|
loop {}
|
||||||
}
|
}
|
||||||
|
|
|
@ -9,14 +9,12 @@ use libboard_zynq::{
|
||||||
println,
|
println,
|
||||||
self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll},
|
self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll},
|
||||||
};
|
};
|
||||||
use libsupport_zynq::{ram, boot};
|
use libsupport_zynq::ram;
|
||||||
use libcortex_a9::{mutex::Mutex, sync_channel::{self, sync_channel}};
|
|
||||||
|
|
||||||
mod comms;
|
mod comms;
|
||||||
mod pl;
|
mod pl;
|
||||||
mod rtio;
|
mod rtio;
|
||||||
mod kernel;
|
mod kernel;
|
||||||
mod control;
|
|
||||||
|
|
||||||
|
|
||||||
fn identifier_read(buf: &mut [u8]) -> &str {
|
fn identifier_read(buf: &mut [u8]) -> &str {
|
||||||
|
@ -32,10 +30,6 @@ fn identifier_read(buf: &mut [u8]) -> &str {
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static mut STACK_CORE1: [u32; 512] = [0; 512];
|
|
||||||
static CHANNEL_0TO1: Mutex<Option<sync_channel::Receiver<usize>>> = Mutex::new(None);
|
|
||||||
static CHANNEL_1TO0: Mutex<Option<sync_channel::Sender<usize>>> = Mutex::new(None);
|
|
||||||
|
|
||||||
#[no_mangle]
|
#[no_mangle]
|
||||||
pub fn main_core0() {
|
pub fn main_core0() {
|
||||||
println!("ARTIQ runtime starting...");
|
println!("ARTIQ runtime starting...");
|
||||||
|
@ -53,22 +47,3 @@ pub fn main_core0() {
|
||||||
|
|
||||||
comms::main();
|
comms::main();
|
||||||
}
|
}
|
||||||
|
|
||||||
#[no_mangle]
|
|
||||||
pub fn main_core1() {
|
|
||||||
println!("Core1 started");
|
|
||||||
|
|
||||||
let mut core1_tx = None;
|
|
||||||
while core1_tx.is_none() {
|
|
||||||
core1_tx = CHANNEL_1TO0.lock().take();
|
|
||||||
}
|
|
||||||
let mut core1_tx = core1_tx.unwrap();
|
|
||||||
|
|
||||||
let mut core1_rx = None;
|
|
||||||
while core1_rx.is_none() {
|
|
||||||
core1_rx = CHANNEL_0TO1.lock().take();
|
|
||||||
}
|
|
||||||
let mut core1_rx = core1_rx.unwrap();
|
|
||||||
|
|
||||||
kernel::main(core1_tx, core1_rx);
|
|
||||||
}
|
|
||||||
|
|
Loading…
Reference in New Issue