forked from M-Labs/artiq-zynq
move build artifacts out of tree
This commit is contained in:
parent
743b0e198d
commit
4464b85ab3
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@ -2,7 +2,4 @@ result
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examples/*.elf
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__pycache__
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src/runtime/src/pl.rs
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src/szl/src/payload.bin
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src/szl/src/payload.bin.lzma
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src/target
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build
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@ -17,7 +17,7 @@ Impure incremental build:
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```shell
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nix-shell
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cd src
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./zc706.py -g # build gateware
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./zc706.py -g ../build/gateware # build gateware
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make # build firmware
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cd ..
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./remote_run.sh -i
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@ -27,14 +27,13 @@ in
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buildPhase = ''
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export XARGO_RUST_SRC="${rustPlatform.rust.rustc.src}/src"
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export CARGO_HOME=$(mktemp -d cargo-home.XXX)
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make clean
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make
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'';
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installPhase = ''
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mkdir -p $out $out/nix-support
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cp target/armv7-none-eabihf/release/runtime $out/runtime.elf
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cp target/armv7-none-eabihf/release/szl $out/szl.elf
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cp ../build/firmware/armv7-none-eabihf/release/runtime $out/runtime.elf
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cp ../build/firmware/armv7-none-eabihf/release/szl $out/szl.elf
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echo file binary-dist $out/runtime.elf >> $out/nix-support/hydra-build-products
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echo file binary-dist $out/szl.elf >> $out/nix-support/hydra-build-products
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'';
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@ -50,7 +49,7 @@ in
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];
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}
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''
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python ${./src/zc706.py} -g
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python ${./src/zc706.py} -g build
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mkdir -p $out $out/nix-support
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cp build/top.bit $out
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echo file binary-dist $out/top.bit >> $out/nix-support/hydra-build-products
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@ -21,8 +21,8 @@ target_folder=/tmp/zynq-\$USER
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ssh $target_host "mkdir -p $target_folder"
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rsync openocd/* $target_host:$target_folder
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if [ $impure -eq 1 ]; then
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rsync src/target/armv7-none-eabihf/release/szl $target_host:$target_folder/szl.elf
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rsync src/build/top.bit $target_host:$target_folder
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rsync build/firmware/armv7-none-eabihf/release/szl $target_host:$target_folder/szl.elf
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rsync build/gateware/top.bit $target_host:$target_folder
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else
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rsync -L result/szl.elf $target_host:$target_folder
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rsync -L result/top.bit $target_host:$target_folder
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29
src/Makefile
29
src/Makefile
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@ -1,23 +1,18 @@
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all: target/armv7-none-eabihf/release/szl
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all: ../build/firmware/armv7-none-eabihf/release/szl
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clean:
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rm -f runtime/src/pl.rs
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rm -f szl/src/payload.bin
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rm -f szl/src/payload.bin.lzma
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rm -rf target
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.PHONY: all clean
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.PHONY: all
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runtime/src/pl.rs: zc706.py
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python zc706.py -r runtime/src/pl.rs
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../build/pl.rs: zc706.py
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mkdir -p ../build
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python zc706.py -r ../build/pl.rs
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target/armv7-none-eabihf/release/runtime: .cargo/* armv7-none-eabihf.json Cargo.lock Cargo.toml libdyld/* libdyld/src/* runtime/* runtime/src/* runtime/src/pl.rs
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cargo xbuild --release -p runtime
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../build/firmware/armv7-none-eabihf/release/runtime: .cargo/* armv7-none-eabihf.json Cargo.lock Cargo.toml libdyld/* libdyld/src/* runtime/* runtime/src/* ../build/pl.rs
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cargo xbuild --release -p runtime --target-dir ../build/firmware
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szl/src/payload.bin.lzma: target/armv7-none-eabihf/release/runtime
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llvm-objcopy -O binary target/armv7-none-eabihf/release/runtime szl/src/payload.bin
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lzma --keep -f szl/src/payload.bin
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../build/szl-payload.bin.lzma: ../build/firmware/armv7-none-eabihf/release/runtime
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llvm-objcopy -O binary ../build/firmware/armv7-none-eabihf/release/runtime ../build/szl-payload.bin
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lzma --keep -f ../build/szl-payload.bin
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target/armv7-none-eabihf/release/szl: .cargo/* armv7-none-eabihf.json Cargo.lock Cargo.toml szl/* szl/src/* szl/src/payload.bin.lzma
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cargo xbuild --release -p szl
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../build/firmware/armv7-none-eabihf/release/szl: .cargo/* armv7-none-eabihf.json Cargo.lock Cargo.toml szl/* szl/src/* ../build/szl-payload.bin.lzma
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cargo xbuild --release -p szl --target-dir ../build/firmware
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@ -13,6 +13,7 @@ use libsupport_zynq::ram;
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mod proto;
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mod comms;
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#[path = "../../../build/pl.rs"]
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mod pl;
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mod rtio;
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mod kernel;
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@ -40,7 +40,7 @@ pub fn main_core0() {
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libboard_zynq::stdio::drop_uart(); // reinitialize UART after clocking change
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let mut ddr = zynq::ddr::DdrRam::new();
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let payload = include_bytes!("payload.bin.lzma");
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let payload = include_bytes!("../../../build/szl-payload.bin.lzma");
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info!("decompressing payload");
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let result = unsafe {
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unlzma_simple(payload.as_ptr(), payload.len() as i32, ddr.ptr(), lzma_error)
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@ -60,15 +60,15 @@ def main():
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description="ARTIQ port to the ZC706 Zynq development kit")
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parser.add_argument("-r", default=None,
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help="build Rust interface into the specified file")
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parser.add_argument("-g", action="store_true",
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help="build gateware")
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parser.add_argument("-g", default=None,
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help="build gateware into the specified directory")
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args = parser.parse_args()
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soc = ZC706()
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soc.finalize()
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if args.g:
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soc.build()
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if args.g is not None:
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soc.build(build_dir=args.g)
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if args.r is not None:
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write_csr_file(soc, args.r)
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