forked from M-Labs/artiq-zynq
DDMTD: replace FD with ISERDESE2
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@ -10,18 +10,44 @@ class DDMTDSampler(Module):
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# # #
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# # #
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ref_beating_FF = Signal()
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ref_clk = Signal()
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main_beating_FF = Signal()
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self.specials +=[
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self.specials += [
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# ISERDESE2 can only be driven from fabric via IDELAYE2 (see UG471)
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# Two back to back FFs are used to prevent metastability
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Instance("IDELAYE2",
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Instance("FD", i_C=ClockSignal("helper"),
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p_DELAY_SRC="DATAIN",
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i_D=cd_ref.clk, o_Q=ref_beating_FF),
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p_HIGH_PERFORMANCE_MODE="TRUE",
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Instance("FD", i_C=ClockSignal("helper"),
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p_REFCLK_FREQUENCY=208.3, # REFCLK frequency from IDELAYCTRL
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i_D=ref_beating_FF, o_Q=self.ref_beating),
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p_IDELAY_VALUE=0,
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Instance("FD", i_C=ClockSignal("helper"),
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i_D=main_clk_se, o_Q=main_beating_FF),
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i_DATAIN=cd_ref.clk,
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Instance("FD", i_C=ClockSignal("helper"),
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i_D=main_beating_FF, o_Q=self.main_beating)
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o_DATAOUT=ref_clk
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),
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Instance("ISERDESE2",
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p_IOBDELAY="IFD", # use DDLY as input
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p_DATA_RATE="SDR",
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p_DATA_WIDTH=2, # min is 2
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p_NUM_CE=1,
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i_DDLY=ref_clk,
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i_CE1=1,
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i_CLK=ClockSignal("helper"),
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i_CLKDIV=ClockSignal("helper"),
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o_Q1=self.ref_beating
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),
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Instance("ISERDESE2",
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p_DATA_RATE="SDR",
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p_DATA_WIDTH=2, # min is 2
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p_NUM_CE=1,
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i_D=main_clk_se,
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i_CE1=1,
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i_CLK=ClockSignal("helper"),
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i_CLKDIV=ClockSignal("helper"),
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o_Q1=self.main_beating,
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),
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]
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]
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