forked from M-Labs/artiq-zynq
aux: increase max payload size
This commit is contained in:
parent
4341d2d2a5
commit
2b2ebb5354
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@ -1,9 +1,10 @@
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use core::slice;
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use core_io::{Error as IoError, ErrorKind as IoErrorKind};
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use core_io::{Error as IoError, ErrorKind as IoErrorKind};
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use crc;
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use crc;
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use io::{proto::{ProtoRead, ProtoWrite},
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use io::{proto::{ProtoRead, ProtoWrite},
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Cursor};
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Cursor};
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use libboard_zynq::{time::Milliseconds, timer::GlobalTimer};
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use libboard_zynq::{time::Milliseconds, timer::GlobalTimer};
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use libcortex_a9::asm::dmb;
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pub use crate::drtioaux_proto::Packet;
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pub use crate::drtioaux_proto::Packet;
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use crate::{drtioaux_proto::Error as ProtocolError, mem::mem::DRTIOAUX_MEM, pl::csr::DRTIOAUX};
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use crate::{drtioaux_proto::Error as ProtocolError, mem::mem::DRTIOAUX_MEM, pl::csr::DRTIOAUX};
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@ -56,19 +57,6 @@ pub fn has_rx_error(linkno: u8) -> bool {
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}
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}
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}
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}
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pub fn copy_work_buffer(src: *mut u32, dst: *mut u32, len: isize) {
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// AXI writes must be 4-byte aligned (drtio proto doesn't care for that),
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// and AXI burst reads/writes are not implemented yet in gateware
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// thus the need for a work buffer for transmitting and copying it over
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unsafe {
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for i in 0..(len / 4) {
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*dst.offset(i) = *src.offset(i);
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//data memory barrier to prevent bursts
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dmb();
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}
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}
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}
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fn receive<F, T>(linkno: u8, f: F) -> Result<Option<T>, Error>
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fn receive<F, T>(linkno: u8, f: F) -> Result<Option<T>, Error>
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where F: FnOnce(&[u8]) -> Result<T, Error> {
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where F: FnOnce(&[u8]) -> Result<T, Error> {
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let linkidx = linkno as usize;
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let linkidx = linkno as usize;
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@ -76,13 +64,7 @@ where F: FnOnce(&[u8]) -> Result<T, Error> {
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if (DRTIOAUX[linkidx].aux_rx_present_read)() == 1 {
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if (DRTIOAUX[linkidx].aux_rx_present_read)() == 1 {
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let read_ptr = (DRTIOAUX[linkidx].aux_read_pointer_read)() as usize;
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let read_ptr = (DRTIOAUX[linkidx].aux_read_pointer_read)() as usize;
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let ptr = (DRTIOAUX_MEM[linkidx].base + DRTIOAUX_MEM[linkidx].size / 2 + read_ptr * 0x400) as *mut u32;
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let ptr = (DRTIOAUX_MEM[linkidx].base + DRTIOAUX_MEM[linkidx].size / 2 + read_ptr * 0x400) as *mut u32;
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// work buffer to accomodate axi burst reads
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let result = f(slice::from_raw_parts(ptr as *mut u8, 0x400 as usize));
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// buffer at maximum proto packet size, not maximum gateware supported size
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// to minimize copying time
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const LEN: usize = 512;
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let mut buf: [u8; LEN] = [0; LEN];
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copy_work_buffer(ptr, buf.as_mut_ptr() as *mut u32, LEN as isize);
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let result = f(&buf);
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(DRTIOAUX[linkidx].aux_rx_present_write)(1);
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(DRTIOAUX[linkidx].aux_rx_present_write)(1);
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Ok(Some(result?))
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Ok(Some(result?))
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} else {
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} else {
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@ -133,10 +115,7 @@ where F: FnOnce(&mut [u8]) -> Result<usize, Error> {
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unsafe {
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unsafe {
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while (DRTIOAUX[linkno].aux_tx_read)() != 0 {}
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while (DRTIOAUX[linkno].aux_tx_read)() != 0 {}
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let ptr = DRTIOAUX_MEM[linkno].base as *mut u32;
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let ptr = DRTIOAUX_MEM[linkno].base as *mut u32;
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// work buffer, works with unaligned mem access
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let len = f(slice::from_raw_parts_mut(ptr as *mut u8, 0x400 as usize))?;
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let mut buf: [u8; 1024] = [0; 1024];
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let len = f(&mut buf)?;
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copy_work_buffer(buf.as_mut_ptr() as *mut u32, ptr, len as isize);
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(DRTIOAUX[linkno].aux_tx_length_write)(len as u16);
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(DRTIOAUX[linkno].aux_tx_length_write)(len as u16);
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(DRTIOAUX[linkno].aux_tx_write)(1);
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(DRTIOAUX[linkno].aux_tx_write)(1);
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Ok(())
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Ok(())
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@ -1,3 +1,5 @@
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use core::slice;
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use core_io::{Error as IoError, ErrorKind as IoErrorKind};
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use core_io::{Error as IoError, ErrorKind as IoErrorKind};
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use crc;
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use crc;
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use io::{proto::{ProtoRead, ProtoWrite},
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use io::{proto::{ProtoRead, ProtoWrite},
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@ -8,7 +10,7 @@ use nb;
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use void::Void;
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use void::Void;
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pub use crate::drtioaux_proto::Packet;
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pub use crate::drtioaux_proto::Packet;
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use crate::{drtioaux::{copy_work_buffer, has_rx_error, Error},
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use crate::{drtioaux::{has_rx_error, Error},
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mem::mem::DRTIOAUX_MEM,
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mem::mem::DRTIOAUX_MEM,
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pl::csr::DRTIOAUX};
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pl::csr::DRTIOAUX};
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@ -40,13 +42,7 @@ where F: FnOnce(&[u8]) -> Result<T, Error> {
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if (DRTIOAUX[linkidx].aux_rx_present_read)() == 1 {
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if (DRTIOAUX[linkidx].aux_rx_present_read)() == 1 {
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let read_ptr = (DRTIOAUX[linkidx].aux_read_pointer_read)() as usize;
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let read_ptr = (DRTIOAUX[linkidx].aux_read_pointer_read)() as usize;
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let ptr = (DRTIOAUX_MEM[linkidx].base + DRTIOAUX_MEM[linkidx].size / 2 + read_ptr * 0x400) as *mut u32;
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let ptr = (DRTIOAUX_MEM[linkidx].base + DRTIOAUX_MEM[linkidx].size / 2 + read_ptr * 0x400) as *mut u32;
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// work buffer to accomodate axi burst reads
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let result = f(slice::from_raw_parts(ptr as *mut u8, 0x400 as usize));
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// buffer at maximum proto packet size, not maximum gateware supported size
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// to minimize required copying time
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const LEN: usize = 512;
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let mut buf: [u8; LEN] = [0; LEN];
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copy_work_buffer(ptr, buf.as_mut_ptr() as *mut u32, LEN as isize);
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let result = f(&buf);
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(DRTIOAUX[linkidx].aux_rx_present_write)(1);
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(DRTIOAUX[linkidx].aux_rx_present_write)(1);
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Ok(Some(result?))
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Ok(Some(result?))
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} else {
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} else {
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@ -106,10 +102,7 @@ where F: FnOnce(&mut [u8]) -> Result<usize, Error> {
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unsafe {
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unsafe {
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let _ = block_async!(tx_ready(linkno)).await;
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let _ = block_async!(tx_ready(linkno)).await;
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let ptr = DRTIOAUX_MEM[linkno].base as *mut u32;
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let ptr = DRTIOAUX_MEM[linkno].base as *mut u32;
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// work buffer, works with unaligned mem access
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let len = f(slice::from_raw_parts_mut(ptr as *mut u8, 0x400 as usize))?;
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let mut buf: [u8; 1024] = [0; 1024];
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let len = f(&mut buf)?;
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copy_work_buffer(buf.as_mut_ptr() as *mut u32, ptr, len as isize);
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(DRTIOAUX[linkno].aux_tx_length_write)(len as u16);
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(DRTIOAUX[linkno].aux_tx_length_write)(len as u16);
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(DRTIOAUX[linkno].aux_tx_write)(1);
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(DRTIOAUX[linkno].aux_tx_write)(1);
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Ok(())
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Ok(())
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@ -1,9 +1,11 @@
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use core_io::{Error as IoError, Read, Write};
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use core_io::{Error as IoError, Read, Write};
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use io::proto::{ProtoRead, ProtoWrite};
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use io::proto::{ProtoRead, ProtoWrite};
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const MAX_PACKET: usize = 1024;
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// maximum size of arbitrary payloads
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// maximum size of arbitrary payloads
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// used by satellite -> master analyzer, subkernel exceptions
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// used by satellite -> master analyzer, subkernel exceptions
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pub const SAT_PAYLOAD_MAX_SIZE: usize = /*max size*/512 - /*CRC*/4 - /*packet ID*/1 - /*last*/1 - /*length*/2;
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pub const SAT_PAYLOAD_MAX_SIZE: usize = /*max size*/MAX_PACKET - /*CRC*/4 - /*packet ID*/1 - /*last*/1 - /*length*/2;
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// used by DDMA, subkernel program data (need to provide extra ID and destination)
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// used by DDMA, subkernel program data (need to provide extra ID and destination)
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pub const MASTER_PAYLOAD_MAX_SIZE: usize = SAT_PAYLOAD_MAX_SIZE - /*source*/1 - /*destination*/1 - /*ID*/4;
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pub const MASTER_PAYLOAD_MAX_SIZE: usize = SAT_PAYLOAD_MAX_SIZE - /*source*/1 - /*destination*/1 - /*ID*/4;
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@ -45,7 +45,10 @@ impl<T: AsRef<[u8]>> Read for Cursor<T> {
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fn read(&mut self, buf: &mut [u8]) -> Result<usize, IoError> {
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fn read(&mut self, buf: &mut [u8]) -> Result<usize, IoError> {
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let data = &self.inner.as_ref()[self.pos..];
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let data = &self.inner.as_ref()[self.pos..];
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let len = buf.len().min(data.len());
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let len = buf.len().min(data.len());
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buf[..len].copy_from_slice(&data[..len]);
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// ``copy_from_slice`` generates AXI bursts, use a regular loop instead
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for i in 0..len {
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buf[i] = data[i];
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}
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self.pos += len;
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self.pos += len;
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Ok(len)
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Ok(len)
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}
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}
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@ -55,7 +58,9 @@ impl Write for Cursor<&mut [u8]> {
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fn write(&mut self, buf: &[u8]) -> Result<usize, IoError> {
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fn write(&mut self, buf: &[u8]) -> Result<usize, IoError> {
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let data = &mut self.inner[self.pos..];
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let data = &mut self.inner[self.pos..];
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let len = buf.len().min(data.len());
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let len = buf.len().min(data.len());
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data[..len].copy_from_slice(&buf[..len]);
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for i in 0..len {
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data[i] = buf[i];
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}
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self.pos += len;
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self.pos += len;
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Ok(len)
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Ok(len)
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}
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}
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@ -68,7 +73,6 @@ impl Write for Cursor<&mut [u8]> {
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#[cfg(feature = "alloc")]
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#[cfg(feature = "alloc")]
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impl Write for Cursor<Vec<u8>> {
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impl Write for Cursor<Vec<u8>> {
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#[inline]
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fn write(&mut self, buf: &[u8]) -> Result<usize, IoError> {
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fn write(&mut self, buf: &[u8]) -> Result<usize, IoError> {
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self.inner.extend_from_slice(buf);
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self.inner.extend_from_slice(buf);
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Ok(buf.len())
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Ok(buf.len())
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