forked from M-Labs/artiq-zynq
Firmware: Runtime WRPLL
runtime: drive CLK_SEL to true when si549 is used runtime & libboard_artiq: allow standalone to use io_expander si549: add bit bang mmcm dynamic configuration si549: add frequency counter for refclk rtio_clocking & si549: add 125Mhz wrpll refclk setup
This commit is contained in:
parent
b81323af30
commit
14fa038118
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@ -22,7 +22,7 @@ pub mod drtioaux;
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pub mod drtioaux_async;
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pub mod drtioaux_proto;
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pub mod fiq;
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#[cfg(all(feature = "target_kasli_soc", has_drtio))]
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#[cfg(feature = "target_kasli_soc")]
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pub mod io_expander;
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pub mod logger;
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#[cfg(has_drtio)]
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@ -673,3 +673,144 @@ pub mod wrpll {
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}
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}
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}
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#[cfg(has_wrpll_refclk)]
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pub mod wrpll_refclk {
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use super::*;
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pub struct MmcmSetting {
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pub clkout0_reg1: u16, //0x08
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pub clkout0_reg2: u16, //0x09
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pub clkfbout_reg1: u16, //0x14
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pub clkfbout_reg2: u16, //0x15
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pub div_reg: u16, //0x16
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pub lock_reg1: u16, //0x18
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pub lock_reg2: u16, //0x19
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pub lock_reg3: u16, //0x1A
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pub power_reg: u16, //0x28
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pub filt_reg1: u16, //0x4E
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pub filt_reg2: u16, //0x4F
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}
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fn one_clock_cycle() {
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unsafe {
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csr::wrpll_refclk::mmcm_dclk_write(1);
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csr::wrpll_refclk::mmcm_dclk_write(0);
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}
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}
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fn set_addr(address: u8) {
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unsafe {
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csr::wrpll_refclk::mmcm_daddr_write(address);
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}
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}
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fn set_data(value: u16) {
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unsafe {
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csr::wrpll_refclk::mmcm_din_write(value);
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}
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}
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fn set_enable(en: bool) {
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unsafe {
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let val = if en { 1 } else { 0 };
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csr::wrpll_refclk::mmcm_den_write(val);
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}
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}
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fn set_write_enable(en: bool) {
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unsafe {
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let val = if en { 1 } else { 0 };
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csr::wrpll_refclk::mmcm_dwen_write(val);
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}
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}
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fn get_data() -> u16 {
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unsafe { csr::wrpll_refclk::mmcm_dout_read() }
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}
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fn drp_ready() -> bool {
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unsafe { csr::wrpll_refclk::mmcm_dready_read() == 1 }
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}
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#[allow(dead_code)]
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fn read(address: u8) -> u16 {
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set_addr(address);
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set_enable(true);
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// Set DADDR on the mmcm and assert DEN for one clock cycle
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one_clock_cycle();
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set_enable(false);
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while !drp_ready() {
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// keep the clock signal until data is ready
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one_clock_cycle();
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}
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get_data()
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}
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fn write(address: u8, value: u16) {
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set_addr(address);
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set_data(value);
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set_write_enable(true);
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set_enable(true);
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// Set DADDR, DI on the mmcm and assert DWE, DEN for one clock cycle
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one_clock_cycle();
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set_write_enable(false);
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set_enable(false);
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while !drp_ready() {
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// keep the clock signal until write is finished
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one_clock_cycle();
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}
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}
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fn reset(rst: bool) {
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unsafe {
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let val = if rst { 1 } else { 0 };
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csr::wrpll_refclk::mmcm_reset_write(val)
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}
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}
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pub fn setup(timer: &mut GlobalTimer, settings: MmcmSetting, mmcm_bypass: bool) -> Result<(), &'static str> {
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unsafe {
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csr::wrpll_refclk::refclk_reset_write(1);
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}
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if mmcm_bypass {
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info!("Bypassing mmcm");
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unsafe {
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csr::wrpll_refclk::mmcm_bypass_write(1);
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}
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} else {
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// Based on "DRP State Machine" from XAPP888
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// hold reset HIGH during mmcm config
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reset(true);
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write(0x08, settings.clkout0_reg1);
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write(0x09, settings.clkout0_reg2);
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write(0x14, settings.clkfbout_reg1);
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write(0x15, settings.clkfbout_reg2);
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write(0x16, settings.div_reg);
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write(0x18, settings.lock_reg1);
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write(0x19, settings.lock_reg2);
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write(0x1A, settings.lock_reg3);
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write(0x28, settings.power_reg);
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write(0x4E, settings.filt_reg1);
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write(0x4F, settings.filt_reg2);
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reset(false);
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// wait for the mmcm to lock
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timer.delay_us(100);
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let locked = unsafe { csr::wrpll_refclk::mmcm_locked_read() == 1 };
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if !locked {
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return Err("mmcm failed to generate 125MHz ref clock from SMA CLKIN");
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}
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}
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unsafe {
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csr::wrpll_refclk::refclk_reset_write(0);
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}
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Ok(())
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}
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}
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@ -8,14 +8,14 @@
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#[macro_use]
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extern crate alloc;
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#[cfg(all(feature = "target_kasli_soc", has_drtio))]
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#[cfg(all(feature = "target_kasli_soc", has_virtual_leds))]
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use core::cell::RefCell;
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use ksupport;
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use libasync::task;
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#[cfg(has_drtio_eem)]
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use libboard_artiq::drtio_eem;
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#[cfg(all(feature = "target_kasli_soc", has_drtio))]
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#[cfg(feature = "target_kasli_soc")]
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use libboard_artiq::io_expander;
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use libboard_artiq::{identifier_read, logger, pl};
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use libboard_zynq::{gic, mpcore, timer::GlobalTimer};
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@ -43,7 +43,7 @@ extern "C" {
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static __exceptions_start: u32;
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}
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#[cfg(all(feature = "target_kasli_soc", has_drtio))]
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#[cfg(all(feature = "target_kasli_soc", has_virtual_leds))]
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async fn io_expanders_service(
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i2c_bus: RefCell<&mut libboard_zynq::i2c::I2c>,
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io_expander0: RefCell<io_expander::IoExpander>,
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@ -101,7 +101,7 @@ pub fn main_core0() {
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info!("gateware ident: {}", identifier_read(&mut [0; 64]));
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ksupport::i2c::init();
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#[cfg(all(feature = "target_kasli_soc", has_drtio))]
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#[cfg(feature = "target_kasli_soc")]
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{
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let i2c_bus = unsafe { (ksupport::i2c::I2C_BUS).as_mut().unwrap() };
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let mut io_expander0 = io_expander::IoExpander::new(i2c_bus, 0).unwrap();
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io_expander1
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.init(i2c_bus)
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.expect("I2C I/O expander #1 initialization failed");
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// Drive CLK_SEL to true
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#[cfg(has_si549)]
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io_expander0.set(1, 7, true);
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// Drive TX_DISABLE to false on SFP0..3
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io_expander0.set(0, 1, false);
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io_expander1.set(0, 1, false);
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io_expander1.set(1, 1, false);
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io_expander0.service(i2c_bus).unwrap();
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io_expander1.service(i2c_bus).unwrap();
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#[cfg(has_virtual_leds)]
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task::spawn(io_expanders_service(
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RefCell::new(i2c_bus),
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RefCell::new(io_expander0),
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@ -4,6 +4,8 @@ use ksupport::i2c;
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use libboard_artiq::pl;
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#[cfg(has_si5324)]
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use libboard_artiq::si5324;
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#[cfg(has_si549)]
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use libboard_artiq::si549;
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#[cfg(has_si5324)]
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use libboard_zynq::i2c::I2c;
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use libboard_zynq::timer::GlobalTimer;
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si5324::setup(i2c, &si5324_settings, si5324_ref_input, timer).expect("cannot initialize Si5324");
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}
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#[cfg(all(has_si549, has_wrpll))]
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fn wrpll_setup(timer: &mut GlobalTimer, clk: RtioClock, si549_settings: &si549::FrequencySetting) {
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// register values are directly copied from preconfigured mmcm
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let (mmcm_setting, mmcm_bypass) = match clk {
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RtioClock::Ext0_Synth0_10to125 => (
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si549::wrpll_refclk::MmcmSetting {
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// CLKFBOUT_MULT = 62.5, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 5
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clkout0_reg1: 0x1083,
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clkout0_reg2: 0x0080,
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clkfbout_reg1: 0x179e,
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clkfbout_reg2: 0x4c00,
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div_reg: 0x1041,
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lock_reg1: 0x00fa,
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lock_reg2: 0x7c01,
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lock_reg3: 0xffe9,
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power_reg: 0x9900,
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filt_reg1: 0x0808,
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filt_reg2: 0x0800,
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},
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false,
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),
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RtioClock::Ext0_Synth0_80to125 => (
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si549::wrpll_refclk::MmcmSetting {
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// CLKFBOUT_MULT = 15.625, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 10
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clkout0_reg1: 0x1145,
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clkout0_reg2: 0x0000,
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clkfbout_reg1: 0x11c7,
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clkfbout_reg2: 0x5880,
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div_reg: 0x1041,
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lock_reg1: 0x028a,
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lock_reg2: 0x7c01,
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lock_reg3: 0xffe9,
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power_reg: 0x9900,
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filt_reg1: 0x0808,
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filt_reg2: 0x9800,
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},
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false,
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),
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RtioClock::Ext0_Synth0_100to125 => (
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si549::wrpll_refclk::MmcmSetting {
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// CLKFBOUT_MULT = 12.5, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 10
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clkout0_reg1: 0x1145,
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clkout0_reg2: 0x0000,
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clkfbout_reg1: 0x1145,
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clkfbout_reg2: 0x4c00,
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div_reg: 0x1041,
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lock_reg1: 0x0339,
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lock_reg2: 0x7c01,
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lock_reg3: 0xffe9,
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power_reg: 0x9900,
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filt_reg1: 0x0808,
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filt_reg2: 0x9800,
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},
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false,
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),
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RtioClock::Ext0_Synth0_125to125 => (
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si549::wrpll_refclk::MmcmSetting {
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// CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 10
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clkout0_reg1: 0x1145,
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clkout0_reg2: 0x0000,
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clkfbout_reg1: 0x1145,
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clkfbout_reg2: 0x0000,
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div_reg: 0x1041,
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lock_reg1: 0x03e8,
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lock_reg2: 0x7001,
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lock_reg3: 0xf3e9,
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power_reg: 0x0100,
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filt_reg1: 0x0808,
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filt_reg2: 0x1100,
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},
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true,
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),
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_ => unreachable!(),
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};
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si549::helper_setup(timer, &si549_settings).expect("cannot initialize helper Si549");
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si549::wrpll_refclk::setup(timer, mmcm_setting, mmcm_bypass).expect("cannot initialize ref clk for wrpll");
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si549::wrpll::select_recovered_clock(true, timer);
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}
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#[cfg(has_si549)]
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fn get_si549_setting(clk: RtioClock) -> si549::FrequencySetting {
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match clk {
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RtioClock::Ext0_Synth0_10to125 => {
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info!("using 10MHz reference to make 125MHz RTIO clock with WRPLL");
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}
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RtioClock::Ext0_Synth0_80to125 => {
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info!("using 80MHz reference to make 125MHz RTIO clock with WRPLL");
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}
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RtioClock::Ext0_Synth0_100to125 => {
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info!("using 100MHz reference to make 125MHz RTIO clock with WRPLL");
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}
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RtioClock::Ext0_Synth0_125to125 => {
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info!("using 125MHz reference to make 125MHz RTIO clock with WRPLL");
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}
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RtioClock::Int_100 => {
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info!("using internal 100MHz RTIO clock");
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}
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RtioClock::Int_125 => {
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info!("using internal 125MHz RTIO clock");
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}
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_ => {
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warn!(
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"rtio_clock setting '{:?}' is unsupported. Falling back to default internal 125MHz RTIO clock.",
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clk
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);
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}
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};
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match clk {
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RtioClock::Int_100 => {
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si549::FrequencySetting {
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main: si549::DividerConfig {
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hsdiv: 0x06C,
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lsdiv: 0,
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fbdiv: 0x046C5F49797,
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},
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helper: si549::DividerConfig {
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// 100MHz*32767/32768
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hsdiv: 0x06C,
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lsdiv: 0,
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fbdiv: 0x046C5670BBD,
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},
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}
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}
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_ => {
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// Everything else use 125MHz
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si549::FrequencySetting {
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main: si549::DividerConfig {
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hsdiv: 0x058,
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lsdiv: 0,
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fbdiv: 0x04815791F25,
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},
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helper: si549::DividerConfig {
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// 125MHz*32767/32768
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hsdiv: 0x058,
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lsdiv: 0,
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fbdiv: 0x04814E8F442,
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},
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}
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}
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}
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}
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pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
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let clk = get_rtio_clock_cfg(cfg);
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#[cfg(has_si5324)]
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@ -274,9 +420,29 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
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}
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}
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#[cfg(has_si549)]
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let si549_settings = get_si549_setting(clk);
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#[cfg(has_si549)]
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si549::main_setup(timer, &si549_settings).expect("cannot initialize main Si549");
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#[cfg(has_drtio)]
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init_drtio(timer);
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#[cfg(not(has_drtio))]
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init_rtio(timer);
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#[cfg(all(has_si549, has_wrpll))]
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{
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// SYS CLK switch will reset CSRs that are used by WRPLL
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match clk {
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RtioClock::Ext0_Synth0_10to125
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| RtioClock::Ext0_Synth0_80to125
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| RtioClock::Ext0_Synth0_100to125
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| RtioClock::Ext0_Synth0_125to125 => {
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wrpll_setup(timer, clk, &si549_settings);
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}
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_ => {}
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}
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}
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}
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