forked from M-Labs/artiq-zynq
kasli-soc: Add BUFG to the IBUFGDS for MMCM CLKIN1
- Fix Vivado Compilation Error [DRC REQP-119] - MMCME2_ADV CLKIN1 and CLKIN2 are now driven from the same source type (BUFG)
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parent
0f050844cf
commit
136e24f597
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@ -127,15 +127,20 @@ class GenericStandalone(SoCCore):
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clk_synth = platform.request("cdr_clk_clean_fabric")
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clk_synth = platform.request("cdr_clk_clean_fabric")
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clk_synth_se = Signal()
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clk_synth_se = Signal()
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clk_synth_se_buf = Signal()
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platform.add_period_constraint(clk_synth.p, 8.0)
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platform.add_period_constraint(clk_synth.p, 8.0)
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self.specials += Instance("IBUFGDS",
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self.specials += [
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Instance("IBUFGDS",
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
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i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se)
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i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se
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),
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Instance("BUFG", i_I=clk_synth_se, o_O=clk_synth_se_buf),
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]
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fix_serdes_timing_path(platform)
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fix_serdes_timing_path(platform)
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self.submodules.bootstrap = GTPBootstrapClock(self.platform, description["rtio_frequency"])
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self.submodules.bootstrap = GTPBootstrapClock(self.platform, description["rtio_frequency"])
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self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, clk_synth_se)
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self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, clk_synth_se_buf)
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platform.add_false_path_constraints(
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platform.add_false_path_constraints(
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self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
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self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
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self.csr_devices.append("sys_crg")
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self.csr_devices.append("sys_crg")
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