forked from M-Labs/artiq-zynq
runtime: encapsulate core1 state in KernelControl
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@ -2,6 +2,7 @@ use core::{mem::transmute, task::Poll};
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use core::fmt;
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use core::fmt;
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use core::cmp::min;
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use core::cmp::min;
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use core::cell::RefCell;
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use core::cell::RefCell;
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use alloc::rc::Rc;
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use num_derive::{FromPrimitive, ToPrimitive};
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use num_derive::{FromPrimitive, ToPrimitive};
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use num_traits::{FromPrimitive, ToPrimitive};
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use num_traits::{FromPrimitive, ToPrimitive};
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@ -21,6 +22,7 @@ use libcortex_a9::sync_channel;
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use libasync::{smoltcp::{Sockets, TcpStream}, task};
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use libasync::{smoltcp::{Sockets, TcpStream}, task};
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use crate::kernel;
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use crate::kernel;
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use crate::control::KernelControl;
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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@ -141,7 +143,7 @@ async fn send_header(stream: &TcpStream, reply: Reply) -> Result<()> {
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Ok(())
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Ok(())
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}
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}
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async fn handle_connection(stream: TcpStream) -> Result<()> {
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async fn handle_connection(stream: TcpStream, control: Rc<RefCell<Option<KernelControl>>>) -> Result<()> {
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expect(&stream, b"ARTIQ coredev\n").await?;
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expect(&stream, b"ARTIQ coredev\n").await?;
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loop {
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loop {
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expect(&stream, &[0x5a, 0x5a, 0x5a, 0x5a]).await?;
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expect(&stream, &[0x5a, 0x5a, 0x5a, 0x5a]).await?;
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@ -163,6 +165,14 @@ async fn handle_connection(stream: TcpStream) -> Result<()> {
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send_header(&stream, Reply::LoadCompleted).await?;
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send_header(&stream, Reply::LoadCompleted).await?;
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}
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}
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println!("length={}, {:?}", length, &kernel_buffer[..256]);
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println!("length={}, {:?}", length, &kernel_buffer[..256]);
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// TODO: dyld
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control.borrow_mut()
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.take()
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.map(|control| control.reset());
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*control.borrow_mut() = Some(KernelControl::start(8192));
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}
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}
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_ => return Err(Error::UnrecognizedPacket)
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_ => return Err(Error::UnrecognizedPacket)
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}
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}
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@ -173,7 +183,7 @@ async fn handle_connection(stream: TcpStream) -> Result<()> {
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const HWADDR: [u8; 6] = [0, 0x23, 0xab, 0xad, 0x1d, 0xea];
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const HWADDR: [u8; 6] = [0, 0x23, 0xab, 0xad, 0x1d, 0xea];
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const IPADDR: IpAddress = IpAddress::Ipv4(Ipv4Address([192, 168, 1, 52]));
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const IPADDR: IpAddress = IpAddress::Ipv4(Ipv4Address([192, 168, 1, 52]));
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pub fn main(mut sc_tx: sync_channel::Sender<usize>, mut sc_rx: sync_channel::Receiver<usize>) {
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pub fn main() {
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let eth = zynq::eth::Eth::default(HWADDR.clone());
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let eth = zynq::eth::Eth::default(HWADDR.clone());
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const RX_LEN: usize = 8;
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const RX_LEN: usize = 8;
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let mut rx_descs = (0..RX_LEN)
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let mut rx_descs = (0..RX_LEN)
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@ -209,11 +219,14 @@ pub fn main(mut sc_tx: sync_channel::Sender<usize>, mut sc_rx: sync_channel::Rec
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Sockets::init(32);
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Sockets::init(32);
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task::spawn(async {
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let control: Rc<RefCell<Option<KernelControl>>> = Rc::new(RefCell::new(None));
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task::spawn(async move {
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loop {
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loop {
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while let stream = TcpStream::accept(1381, 2048, 2048).await.unwrap() {
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while let stream = TcpStream::accept(1381, 2048, 2048).await.unwrap() {
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let control = control.clone();
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task::spawn(async {
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task::spawn(async {
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let _ = handle_connection(stream)
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let _ = handle_connection(stream, control)
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.await
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.await
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.map_err(|e| println!("Connection: {}", e));
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.map_err(|e| println!("Connection: {}", e));
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});
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});
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@ -0,0 +1,38 @@
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use alloc::{vec, vec::Vec};
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use libcortex_a9::{mutex::Mutex, sync_channel::{self, sync_channel}};
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use libsupport_zynq::boot::Core1;
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pub static CHANNEL_0TO1: Mutex<Option<sync_channel::Receiver<usize>>> = Mutex::new(None);
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pub static CHANNEL_1TO0: Mutex<Option<sync_channel::Sender<usize>>> = Mutex::new(None);
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/// Interface for core 0 to control core 1 start and reset
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pub struct KernelControl {
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core1: Core1<Vec<u32>>,
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pub tx: sync_channel::Sender<usize>,
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pub rx: sync_channel::Receiver<usize>,
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}
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impl KernelControl {
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pub fn start(stack_size: usize) -> Self {
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let stack = vec![0; stack_size / 4];
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let core1 = Core1::start(stack);
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let (core0_tx, core1_rx) = sync_channel(4);
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let (core1_tx, core0_rx) = sync_channel(4);
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*CHANNEL_0TO1.lock() = Some(core1_rx);
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*CHANNEL_1TO0.lock() = Some(core1_tx);
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KernelControl {
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core1,
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tx: core0_tx,
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rx: core0_rx,
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}
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}
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pub fn reset(self) {
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*CHANNEL_0TO1.lock() = None;
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*CHANNEL_1TO0.lock() = None;
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self.core1.reset();
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}
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}
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@ -16,6 +16,7 @@ mod comms;
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mod pl;
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mod pl;
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mod rtio;
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mod rtio;
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mod kernel;
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mod kernel;
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mod control;
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fn identifier_read(buf: &mut [u8]) -> &str {
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fn identifier_read(buf: &mut [u8]) -> &str {
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@ -50,15 +51,7 @@ pub fn main_core0() {
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println!("Detected gateware: {}", identifier_read(&mut [0; 64]));
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println!("Detected gateware: {}", identifier_read(&mut [0; 64]));
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let core1_stack = unsafe { &mut STACK_CORE1[..] };
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comms::main();
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let core1 = boot::Core1::start(core1_stack);
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let (mut core0_tx, core1_rx) = sync_channel(4);
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let (core1_tx, mut core0_rx) = sync_channel(4);
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*CHANNEL_0TO1.lock() = Some(core1_rx);
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*CHANNEL_1TO0.lock() = Some(core1_tx);
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comms::main(core0_tx, core0_rx);
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}
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}
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#[no_mangle]
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#[no_mangle]
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