forked from M-Labs/artiq-zynq
kasli-soc: preliminary si5324 support
This commit is contained in:
parent
ce9d38827b
commit
0ae2138034
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@ -1,11 +1,9 @@
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#[cfg(feature = "target_zc706")]
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mod i2c {
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use libboard_zynq;
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use crate::artiq_raise;
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use libboard_zynq;
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use crate::artiq_raise;
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static mut I2C_BUS: Option<libboard_zynq::i2c::I2c> = None;
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pub static mut I2C_BUS: Option<libboard_zynq::i2c::I2c> = None;
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pub extern fn start(busno: i32) {
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pub extern fn start(busno: i32) {
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if busno > 0 {
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artiq_raise!("I2CError", "I2C bus could not be accessed");
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}
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@ -14,9 +12,9 @@ mod i2c {
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artiq_raise!("I2CError", "I2C start failed");
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}
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}
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}
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}
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pub extern fn restart(busno: i32) {
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pub extern fn restart(busno: i32) {
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if busno > 0 {
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artiq_raise!("I2CError", "I2C bus could not be accessed");
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}
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@ -25,9 +23,9 @@ mod i2c {
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artiq_raise!("I2CError", "I2C restart failed");
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}
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}
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}
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}
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pub extern fn stop(busno: i32) {
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pub extern fn stop(busno: i32) {
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if busno > 0 {
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artiq_raise!("I2CError", "I2C bus could not be accessed");
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}
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@ -36,9 +34,9 @@ mod i2c {
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artiq_raise!("I2CError", "I2C stop failed");
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}
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}
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}
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}
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pub extern fn write(busno: i32, data: i32) -> bool {
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pub extern fn write(busno: i32, data: i32) -> bool {
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if busno > 0 {
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artiq_raise!("I2CError", "I2C bus could not be accessed");
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}
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@ -48,9 +46,9 @@ mod i2c {
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Err(_) => artiq_raise!("I2CError", "I2C write failed"),
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}
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}
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}
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}
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pub extern fn read(busno: i32, ack: bool) -> i32 {
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pub extern fn read(busno: i32, ack: bool) -> i32 {
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if busno > 0 {
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artiq_raise!("I2CError", "I2C bus could not be accessed");
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}
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@ -60,41 +58,10 @@ mod i2c {
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Err(_) => artiq_raise!("I2CError", "I2C read failed"),
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}
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}
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}
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}
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pub fn init() {
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pub fn init() {
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let mut i2c = libboard_zynq::i2c::I2c::i2c0();
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i2c.init().expect("I2C bus initialization failed");
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unsafe { I2C_BUS = Some(i2c) };
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}
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}
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#[cfg(not(feature = "target_zc706"))]
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mod i2c {
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use crate::artiq_raise;
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pub extern fn start(_busno: i32) {
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artiq_raise!("I2CError", "No I2C bus");
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}
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pub extern fn restart(_busno: i32) {
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artiq_raise!("I2CError", "No I2C bus");
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}
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pub extern fn stop(_busno: i32) {
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artiq_raise!("I2CError", "No I2C bus");
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}
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pub extern fn write(_busno: i32, _data: i32) -> bool {
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artiq_raise!("I2CError", "No I2C bus");
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}
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pub extern fn read(_busno: i32, _ack: bool) -> i32 {
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artiq_raise!("I2CError", "No I2C bus");
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}
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pub fn init() {
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}
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}
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pub use i2c::*;
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@ -45,6 +45,8 @@ mod mgmt;
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mod analyzer;
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mod irq;
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mod i2c;
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#[cfg(feature = "target_kasli_soc")]
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mod si5324;
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fn init_gateware() {
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// Set up PS->PL clocks
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@ -160,6 +162,20 @@ async fn report_async_rtio_errors() {
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}
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}
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#[cfg(feature = "target_kasli_soc")]
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// 125MHz output, from crystal, 7 Hz
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const SI5324_SETTINGS: si5324::FrequencySettings
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= si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 19972,
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n31 : 4565,
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n32 : 4565,
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bwsel : 4,
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crystal_ref: true
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};
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static mut LOG_BUFFER: [u8; 1<<17] = [0; 1<<17];
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#[no_mangle]
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@ -183,6 +199,9 @@ pub fn main_core0() {
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info!("detected gateware: {}", identifier_read(&mut [0; 64]));
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i2c::init();
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#[cfg(feature = "target_kasli_soc")]
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si5324::setup(unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() },
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&SI5324_SETTINGS, si5324::Input::Ckin1).expect("cannot initialize Si5324");
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let cfg = match Config::new() {
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Ok(cfg) => cfg,
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@ -0,0 +1,258 @@
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use core::result;
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use log::info;
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use libboard_zynq::i2c::I2c;
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type Result<T> = result::Result<T, &'static str>;
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const ADDRESS: u8 = 0x68;
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// NOTE: the logical parameters DO NOT MAP to physical values written
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// into registers. They have to be mapped; see the datasheet.
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// DSPLLsim reports the logical parameters in the design summary, not
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// the physical register values.
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pub struct FrequencySettings {
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pub n1_hs: u8,
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pub nc1_ls: u32,
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pub n2_hs: u8,
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pub n2_ls: u32,
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pub n31: u32,
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pub n32: u32,
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pub bwsel: u8,
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pub crystal_ref: bool
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}
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pub enum Input {
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Ckin1,
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Ckin2,
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}
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fn map_frequency_settings(settings: &FrequencySettings) -> Result<FrequencySettings> {
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if settings.nc1_ls != 0 && (settings.nc1_ls % 2) == 1 {
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return Err("NC1_LS must be 0 or even")
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}
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if settings.nc1_ls > (1 << 20) {
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return Err("NC1_LS is too high")
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}
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if (settings.n2_ls % 2) == 1 {
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return Err("N2_LS must be even")
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}
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if settings.n2_ls > (1 << 20) {
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return Err("N2_LS is too high")
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}
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if settings.n31 > (1 << 19) {
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return Err("N31 is too high")
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}
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if settings.n32 > (1 << 19) {
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return Err("N32 is too high")
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}
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let r = FrequencySettings {
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n1_hs: match settings.n1_hs {
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4 => 0b000,
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5 => 0b001,
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6 => 0b010,
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7 => 0b011,
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8 => 0b100,
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9 => 0b101,
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10 => 0b110,
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11 => 0b111,
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_ => return Err("N1_HS has an invalid value")
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},
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nc1_ls: settings.nc1_ls - 1,
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n2_hs: match settings.n2_hs {
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4 => 0b000,
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5 => 0b001,
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6 => 0b010,
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7 => 0b011,
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8 => 0b100,
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9 => 0b101,
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10 => 0b110,
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11 => 0b111,
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_ => return Err("N2_HS has an invalid value")
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},
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n2_ls: settings.n2_ls - 1,
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n31: settings.n31 - 1,
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n32: settings.n32 - 1,
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bwsel: settings.bwsel,
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crystal_ref: settings.crystal_ref
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};
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Ok(r)
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}
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fn write(i2c: &mut I2c, reg: u8, val: u8) -> Result<()> {
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i2c.start().unwrap();
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if !i2c.write(ADDRESS << 1).unwrap() {
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return Err("Si5324 failed to ack write address")
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}
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if !i2c.write(reg).unwrap() {
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return Err("Si5324 failed to ack register")
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}
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if !i2c.write(val).unwrap() {
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return Err("Si5324 failed to ack value")
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}
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i2c.stop().unwrap();
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Ok(())
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}
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fn write_no_ack_value(i2c: &mut I2c, reg: u8, val: u8) -> Result<()> {
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i2c.start().unwrap();
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if !i2c.write(ADDRESS << 1).unwrap() {
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return Err("Si5324 failed to ack write address")
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}
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if !i2c.write(reg).unwrap() {
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return Err("Si5324 failed to ack register")
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}
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i2c.write(val).unwrap();
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i2c.stop().unwrap();
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Ok(())
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}
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fn read(i2c: &mut I2c, reg: u8) -> Result<u8> {
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i2c.start().unwrap();
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if !i2c.write(ADDRESS << 1).unwrap() {
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return Err("Si5324 failed to ack write address")
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}
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if !i2c.write(reg).unwrap() {
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return Err("Si5324 failed to ack register")
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}
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i2c.restart().unwrap();
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if !i2c.write((ADDRESS << 1) | 1).unwrap() {
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return Err("Si5324 failed to ack read address")
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}
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let val = i2c.read(false).unwrap();
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i2c.stop().unwrap();
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Ok(val)
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}
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fn rmw<F>(i2c: &mut I2c, reg: u8, f: F) -> Result<()> where
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F: Fn(u8) -> u8 {
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let value = read(i2c, reg)?;
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write(i2c, reg, f(value))?;
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Ok(())
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}
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fn ident(i2c: &mut I2c) -> Result<u16> {
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Ok(((read(i2c, 134)? as u16) << 8) | (read(i2c, 135)? as u16))
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}
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fn soft_reset(i2c: &mut I2c) -> Result<()> {
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//TODO write_no_ack_value(i2c, 136, read(136)? | 0x80)?;
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//TODO clock::spin_us(10_000);
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Ok(())
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}
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fn has_xtal(i2c: &mut I2c) -> Result<bool> {
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Ok((read(i2c, 129)? & 0x01) == 0) // LOSX_INT=0
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}
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fn has_ckin(i2c: &mut I2c, input: Input) -> Result<bool> {
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match input {
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Input::Ckin1 => Ok((read(i2c, 129)? & 0x02) == 0), // LOS1_INT=0
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Input::Ckin2 => Ok((read(i2c, 129)? & 0x04) == 0), // LOS2_INT=0
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}
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}
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fn locked(i2c: &mut I2c) -> Result<bool> {
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Ok((read(i2c, 130)? & 0x01) == 0) // LOL_INT=0
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}
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fn monitor_lock(i2c: &mut I2c) -> Result<()> {
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info!("waiting for Si5324 lock...");
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// TODO let t = clock::get_ms();
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while !locked(i2c)? {
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// Yes, lock can be really slow.
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/*if clock::get_ms() > t + 20000 {
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return Err("Si5324 lock timeout");
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}*/
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}
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info!(" ...locked");
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Ok(())
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}
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fn init(i2c: &mut I2c) -> Result<()> {
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info!("init test");
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#[cfg(feature = "target_kasli_soc")]
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{
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i2c.pca9548_select(0x70, 0)?;
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i2c.pca9548_select(0x71, 1 << 3)?;
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}
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if ident(i2c)? != 0x0182 {
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return Err("Si5324 does not have expected product number");
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}
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soft_reset(i2c)?;
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Ok(())
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}
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pub fn bypass(i2c: &mut I2c, input: Input) -> Result<()> {
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let cksel_reg = match input {
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Input::Ckin1 => 0b00,
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Input::Ckin2 => 0b01,
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};
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init(i2c)?;
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rmw(i2c, 21, |v| v & 0xfe)?; // CKSEL_PIN=0
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rmw(i2c, 3, |v| (v & 0x3f) | (cksel_reg << 6))?; // CKSEL_REG
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rmw(i2c, 4, |v| (v & 0x3f) | (0b00 << 6))?; // AUTOSEL_REG=b00
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rmw(i2c, 6, |v| (v & 0xc0) | 0b111111)?; // SFOUT2_REG=b111 SFOUT1_REG=b111
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rmw(i2c, 0, |v| (v & 0xfd) | 0x02)?; // BYPASS_REG=1
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Ok(())
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}
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pub fn setup(i2c: &mut I2c, settings: &FrequencySettings, input: Input) -> Result<()> {
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let s = map_frequency_settings(settings)?;
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let cksel_reg = match input {
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Input::Ckin1 => 0b00,
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Input::Ckin2 => 0b01,
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};
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init(i2c)?;
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if settings.crystal_ref {
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rmw(i2c, 0, |v| v | 0x40)?; // FREE_RUN=1
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}
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rmw(i2c, 2, |v| (v & 0x0f) | (s.bwsel << 4))?;
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rmw(i2c, 21, |v| v & 0xfe)?; // CKSEL_PIN=0
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rmw(i2c, 3, |v| (v & 0x2f) | (cksel_reg << 6) | 0x10)?; // CKSEL_REG, SQ_ICAL=1
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rmw(i2c, 4, |v| (v & 0x3f) | (0b00 << 6))?; // AUTOSEL_REG=b00
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rmw(i2c, 6, |v| (v & 0xc0) | 0b111111)?; // SFOUT2_REG=b111 SFOUT1_REG=b111
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write(i2c, 25, (s.n1_hs << 5 ) as u8)?;
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write(i2c, 31, (s.nc1_ls >> 16) as u8)?;
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write(i2c, 32, (s.nc1_ls >> 8 ) as u8)?;
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write(i2c, 33, (s.nc1_ls) as u8)?;
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write(i2c, 34, (s.nc1_ls >> 16) as u8)?; // write to NC2_LS as well
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write(i2c, 35, (s.nc1_ls >> 8 ) as u8)?;
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write(i2c, 36, (s.nc1_ls) as u8)?;
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write(i2c, 40, (s.n2_hs << 5 ) as u8 | (s.n2_ls >> 16) as u8)?;
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write(i2c, 41, (s.n2_ls >> 8 ) as u8)?;
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write(i2c, 42, (s.n2_ls) as u8)?;
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write(i2c, 43, (s.n31 >> 16) as u8)?;
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write(i2c, 44, (s.n31 >> 8) as u8)?;
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write(i2c, 45, (s.n31) as u8)?;
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write(i2c, 46, (s.n32 >> 16) as u8)?;
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write(i2c, 47, (s.n32 >> 8) as u8)?;
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write(i2c, 48, (s.n32) as u8)?;
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rmw(i2c, 137, |v| v | 0x01)?; // FASTLOCK=1
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rmw(i2c, 136, |v| v | 0x40)?; // ICAL=1
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if !has_xtal(i2c)? {
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return Err("Si5324 misses XA/XB signal");
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}
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if !has_ckin(i2c, input)? {
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return Err("Si5324 misses clock input signal");
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}
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monitor_lock(i2c)?;
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Ok(())
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}
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pub fn select_input(i2c: &mut I2c, input: Input) -> Result<()> {
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let cksel_reg = match input {
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Input::Ckin1 => 0b00,
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Input::Ckin2 => 0b01,
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};
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rmw(i2c, 3, |v| (v & 0x3f) | (cksel_reg << 6))?;
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if !has_ckin(i2c, input)? {
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return Err("Si5324 misses clock input signal");
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}
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monitor_lock(i2c)?;
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Ok(())
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}
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