forked from M-Labs/artiq-zynq
acpki: working
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01093f02cf
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@ -7,8 +7,7 @@ from misoc.interconnect.csr import *
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from artiq.gateware import rtio
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OUT_BURST_LEN = 4
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OUT_BURST_LEN = 10
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IN_BURST_LEN = 4
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@ -98,7 +97,7 @@ class Engine(Module, AutoCSR):
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### Write
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self.comb += [
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w.data.eq(self.din),
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aw.addr.eq(self.addr_base.storage+32), # Write to next cache line
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aw.addr.eq(self.addr_base.storage+96),
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w.strb.eq(0xff),
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aw.burst.eq(axi.Burst.incr.value),
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aw.len.eq(IN_BURST_LEN-1), # Number of transfers in burst minus 1
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@ -191,22 +190,31 @@ class KernelInitiator(Module, AutoCSR):
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cmd_read.eq(cmd == 1)
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]
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out_len = Signal(8)
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dout_cases = {}
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dout_cases[0] = [
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cmd.eq(self.engine.dout[:8]),
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out_len.eq(self.engine.dout[8:16]),
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cri.chan_sel.eq(self.engine.dout[40:]),
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cri.o_address.eq(self.engine.dout[32:40])
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]
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for i in range(8):
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target = cri.o_data[i*64:(i+1)*64]
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dout_cases[0] += [If(i >= self.engine.dout[8:16], target.eq(0))]
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dout_cases[1] = [
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cri.o_timestamp.eq(self.engine.dout)
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cri.o_timestamp.eq(self.engine.dout),
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cri.i_timeout.eq(self.engine.dout)
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]
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dout_cases[2] = [cri.o_data.eq(self.engine.dout)] # only lowest 64 bits
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for i in range(8):
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target = cri.o_data[i*64:(i+1)*64]
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dout_cases[i+2] = [target.eq(self.engine.dout)]
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self.sync += [
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cri.cmd.eq(rtio.cri.commands["nop"]),
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If(self.engine.dout_stb,
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Case(self.engine.dout_index, dout_cases),
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If(self.engine.dout_index == 2,
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If(self.engine.dout_index == out_len + 2,
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If(cmd_write, cri.cmd.eq(rtio.cri.commands["write"])),
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If(cmd_read, cri.cmd.eq(rtio.cri.commands["read"]))
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)
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@ -226,7 +234,11 @@ class KernelInitiator(Module, AutoCSR):
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)
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fsm.act("WAIT_OUT_CYCLE",
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self.engine.din_ready.eq(0),
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If(self.engine.dout_stb & (self.engine.dout_index == 3),
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If(self.engine.dout_stb & cmd_write & (self.engine.dout_index == out_len + 2),
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NextState("WAIT_READY")
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),
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# for some reason read requires some delay until the next state
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If(self.engine.dout_stb & cmd_read & (self.engine.dout_index == out_len + 3),
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NextState("WAIT_READY")
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)
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)
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@ -1,8 +1,8 @@
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use cslice::CSlice;
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use vcell::VolatileCell;
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use libcortex_a9::asm;
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use crate::artiq_raise;
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use core::sync::atomic::{fence, Ordering};
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use crate::pl::csr;
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@ -20,33 +20,33 @@ pub struct TimestampedData {
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data: i32,
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}
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#[repr(C, align(32))]
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#[repr(C, align(64))]
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struct Transaction {
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request_cmd: i8,
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padding0: i8,
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padding1: i8,
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padding2: i8,
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data_width: i8,
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padding0: [i8; 2],
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request_target: i32,
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request_timestamp: i64,
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request_data: i64,
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padding: i64,
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request_data: [i32; 16],
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padding1: [i64; 2],
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reply_status: VolatileCell<i32>,
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reply_data: VolatileCell<i32>,
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reply_timestamp: VolatileCell<i64>
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reply_timestamp: VolatileCell<i64>,
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padding2: [i64; 2],
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}
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static mut TRANSACTION_BUFFER: Transaction = Transaction {
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request_cmd: 0,
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padding0: 0,
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padding1: 0,
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padding2: 0,
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data_width: 0,
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request_target: 0,
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request_timestamp: 0,
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request_data: 0,
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padding: 0,
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request_data: [0; 16],
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reply_status: VolatileCell::new(0),
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reply_data: VolatileCell::new(0),
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reply_timestamp: VolatileCell::new(0)
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reply_timestamp: VolatileCell::new(0),
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padding0: [0; 2],
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padding1: [0; 2],
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padding2: [0; 2]
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};
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pub extern fn init() {
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@ -108,13 +108,41 @@ pub extern fn output(target: i32, data: i32) {
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TRANSACTION_BUFFER.reply_status.set(0);
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TRANSACTION_BUFFER.request_cmd = 0;
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TRANSACTION_BUFFER.data_width = 1;
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TRANSACTION_BUFFER.request_target = target;
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TRANSACTION_BUFFER.request_timestamp = NOW;
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TRANSACTION_BUFFER.request_data = data as i64;
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TRANSACTION_BUFFER.request_data[0] = data;
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asm::dmb();
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fence(Ordering::SeqCst);
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asm::sev();
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let mut status;
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loop {
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status = TRANSACTION_BUFFER.reply_status.get();
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if status != 0 {
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break;
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}
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}
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let status = status & !0x10000;
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if status != 0 {
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process_exceptional_status(target >> 8, status);
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}
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}
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}
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pub extern fn output_wide(target: i32, data: CSlice<i32>) {
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unsafe {
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// Clear status so we can observe response
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TRANSACTION_BUFFER.reply_status.set(0);
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TRANSACTION_BUFFER.request_cmd = 0;
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TRANSACTION_BUFFER.data_width = data.len() as i8;
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TRANSACTION_BUFFER.request_target = target;
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TRANSACTION_BUFFER.request_timestamp = NOW;
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TRANSACTION_BUFFER.request_data[..data.len()].copy_from_slice(data.as_ref());
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fence(Ordering::SeqCst);
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asm::sev();
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let mut status;
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loop {
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status = TRANSACTION_BUFFER.reply_status.get();
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@ -130,21 +158,17 @@ pub extern fn output(target: i32, data: i32) {
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}
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}
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pub extern fn output_wide(target: i32, data: CSlice<i32>) {
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// TODO
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unimplemented!();
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}
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pub extern fn input_timestamp(timeout: i64, channel: i32) -> i64 {
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unsafe {
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// Clear status so we can observe response
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TRANSACTION_BUFFER.reply_status.set(0);
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TRANSACTION_BUFFER.request_cmd = 1;
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TRANSACTION_BUFFER.request_timestamp = NOW;
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TRANSACTION_BUFFER.request_timestamp = timeout;
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TRANSACTION_BUFFER.request_target = channel << 8;
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TRANSACTION_BUFFER.data_width = 0;
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asm::dmb();
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fence(Ordering::SeqCst);
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asm::sev();
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let mut status;
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@ -180,8 +204,9 @@ pub extern fn input_data(channel: i32) -> i32 {
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TRANSACTION_BUFFER.request_cmd = 1;
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TRANSACTION_BUFFER.request_timestamp = -1;
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TRANSACTION_BUFFER.request_target = channel << 8;
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TRANSACTION_BUFFER.data_width = 0;
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asm::dmb();
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fence(Ordering::SeqCst);
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asm::sev();
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let mut status;
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@ -214,8 +239,9 @@ pub extern fn input_timestamped_data(timeout: i64, channel: i32) -> TimestampedD
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TRANSACTION_BUFFER.request_cmd = 1;
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TRANSACTION_BUFFER.request_timestamp = timeout;
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TRANSACTION_BUFFER.request_target = channel << 8;
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TRANSACTION_BUFFER.data_width = 0;
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asm::dmb();
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fence(Ordering::SeqCst);
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asm::sev();
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let mut status;
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@ -245,6 +271,17 @@ pub extern fn input_timestamped_data(timeout: i64, channel: i32) -> TimestampedD
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}
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pub fn write_log(data: &[i8]) {
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// TODO
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unimplemented!();
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let mut word: u32 = 0;
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for i in 0..data.len() {
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word <<= 8;
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word |= data[i] as u32;
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if i % 4 == 3 {
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output((csr::CONFIG_RTIO_LOG_CHANNEL << 8) as i32, word as i32);
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word = 0;
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}
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}
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if word != 0 {
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output((csr::CONFIG_RTIO_LOG_CHANNEL << 8) as i32, word as i32);
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}
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}
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