forked from M-Labs/humpback-dds
92 lines
2.7 KiB
Rust
92 lines
2.7 KiB
Rust
use embedded_hal::{
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digital::v2::{OutputPin, InputPin},
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blocking::spi::Transfer,
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blocking::delay::DelayUs,
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};
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use log::info;
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#[derive(Debug)]
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pub enum FPGAFlashError {
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SPICommunicationError,
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NegotiationError,
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ResetStatusError,
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}
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// A public method to flash iCE40 FPGA on Humpback
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pub fn flash_ice40_fpga<SPI: Transfer<u8>,
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SS: OutputPin,
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RST: OutputPin,
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DELAY: DelayUs<u32>,
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DONE: InputPin>
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(mut spi: SPI, mut ss: SS, mut creset: RST, cdone: DONE, mut delay: DELAY, data: &[u8]) -> Result<(), FPGAFlashError>
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{
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// Data buffer setup
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let mut dummy_byte :[u8; 1] = [0x00];
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let mut dummy_13_bytes :[u8; 13] = [0x00; 13];
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// Drive CRESET_B low
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creset.set_low()
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.map_err(|_| FPGAFlashError::NegotiationError)?;
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// Drive SPI_SS_B low
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ss.set_low()
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.map_err(|_| FPGAFlashError::NegotiationError)?;
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// Wait at least 200ns
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delay.delay_us(1_u32);
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// Drive CRESET_B high
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creset.set_high()
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.map_err(|_| FPGAFlashError::NegotiationError)?;
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// Wait at least another 1200us to clear internal config memory
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delay.delay_us(1200_u32);
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// Before data transmission starts, check if C_DONE is truly low
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// If C_DONE is high, the FPGA reset procedure is unsuccessful
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match cdone.is_low() {
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Ok(true) => {},
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_ => return Err(FPGAFlashError::ResetStatusError),
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};
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// Set SPI_SS_B high
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ss.set_high()
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.map_err(|_| FPGAFlashError::NegotiationError)?;
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// Send 8 dummy clock, effectively 1 byte of 0x00
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spi.transfer(&mut dummy_byte)
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.map_err(|_| FPGAFlashError::SPICommunicationError)?;
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// Drive SPI_SS_B low
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ss.set_low()
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.map_err(|_| FPGAFlashError::NegotiationError)?;
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// Send the whole image without interruption
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for byte in data.into_iter() {
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let mut single_byte_slice = [*byte];
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spi.transfer(&mut single_byte_slice)
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.map_err(|_| FPGAFlashError::SPICommunicationError)?;
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}
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// Drive SPI_SS_B high
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ss.set_high()
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.map_err(|_| FPGAFlashError::NegotiationError)?;
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// Send at another 100 dummy clocks (choosing 13 bytes)
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spi.transfer(&mut dummy_13_bytes)
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.map_err(|_| FPGAFlashError::SPICommunicationError)?;
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// Check the CDONE output from FPGA
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// CDONE needs to be high
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match cdone.is_high() {
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Ok(true) => {},
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_ => return Err(FPGAFlashError::ResetStatusError),
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};
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info!("Configuration successful!");
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// Send at least another 49 clock cycles to activate IO pins (choosing same 13 bytes)
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spi.transfer(&mut dummy_13_bytes).map_err(|_| FPGAFlashError::SPICommunicationError)?;
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info!("User I/O pins activated.");
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Ok(())
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} |