forked from M-Labs/humpback-dds
76 lines
1.8 KiB
Python
76 lines
1.8 KiB
Python
from humpback import HumpbackPlatform
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from migen.fhdl.module import Module
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from migen.fhdl.specials import Instance
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from migen.fhdl.bitcontainer import value_bits_sign
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from migen.genlib.io import *
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from migen.build.lattice.common import LatticeiCE40DifferentialInputImpl
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from migen.genlib.io import DifferentialInput
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class UrukulConnector(Module):
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def __init__(self, platform):
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# Request EEM I/O & SPI
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eem0 = [
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platform.request("eem0", 0),
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platform.request("eem0", 1),
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platform.request("eem0_n", 2),
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platform.request("eem0", 3),
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platform.request("eem0", 4),
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platform.request("eem0", 5),
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platform.request("eem0", 6)
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]
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spi = platform.request("spi")
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led = platform.request("user_led")
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io_update = platform.request("io_update")
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# Assert SPI resource length
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assert len(spi.sclk) == 1
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assert len(spi.mosi) == 1
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assert len(spi.miso) == 1
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assert len(spi.cs) == 3
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# TODO: Assert EEM resources
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assert isinstance(eem0, list)
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# Flip positive signal as negative output, maybe only do it for FPGA outputs
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self.miso_n = Signal()
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# Very similar setup to Diff setup for iCE40 suggested, but gave B pin instead
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self.specials += Instance("SB_IO",
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p_PIN_TYPE=C(0b000001, 6),
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p_IO_STANDARD="SB_LVDS_INPUT",
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io_PACKAGE_PIN=eem0[2],
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o_D_IN_0=self.miso_n
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)
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# Link EEM to SPI
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self.comb += [
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eem0[0].p.eq(spi.sclk),
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eem0[0].n.eq(~spi.sclk),
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eem0[1].p.eq(spi.mosi),
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eem0[1].n.eq(~spi.mosi),
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spi.miso.eq(~self.miso_n),
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eem0[3].p.eq(spi.cs[0]),
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eem0[3].n.eq(~spi.cs[0]),
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eem0[4].p.eq(spi.cs[1]),
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eem0[4].n.eq(~spi.cs[1]),
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eem0[5].p.eq(spi.cs[2]),
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eem0[5].n.eq(~spi.cs[2]),
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eem0[6].p.eq(io_update),
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eem0[6].n.eq(~io_update),
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led.eq(1)
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]
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if __name__ == "__main__":
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platform = HumpbackPlatform()
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platform.build(UrukulConnector(platform))
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