forked from M-Labs/humpback-dds
323 lines
7.5 KiB
Python
323 lines
7.5 KiB
Python
# Strongly inspired by the migen build of humpback
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# Using STM32 Nucleo-H743ZI2 board
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# Note to self: Pin assignment differs from Nucleo-H743ZI
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import os
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import subprocess
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from nmigen.build import *
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from nmigen.vendor.lattice_ice40 import *
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from nmigen_boards.resources import *
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from resources import *
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__all__ = ["HumpbackPlatform"]
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class HumpbackPlatform(LatticeICE40Platform):
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device = "iCE40HX8K" # Using ICE40HX8K-CT256
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package = "CT256"
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default_clk = "clk25"
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resources = [
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# Define clock
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Resource("clk25", 0, Pins("K9", dir="i"),
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Clock(25e6), Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS")
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),
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# Define user LED
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Resource("user_led", 0, Pins("H3", dir="o"),
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Attrs(IO_STANDARD="SB_LVCMOS")
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),
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# TODO: Define UART interfaces somewhere else, make it optional
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UARTResource(0,
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rx="T11", tx="M13", rts="M15", cts="T10",
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attrs=Attrs(IO_STANDARD="SB_LVCMOS", PULLUP=1)
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),
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# UART1 interface: Read note for UART interface above
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# UART1 interface is broken due to pin rearrangement introduced for Nucleo-H743ZI2
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# Uncomment if fixed, or found an alternative (e.g. bit banging UART)
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# *UARTResource(1,
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# tx="M11", rx="T13", rts="A6", cts="B16",
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# attrs=Attrs(IO_STANDARD="SB_LVCMOS", PULLUP=1)
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# ),
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# Define SPI interfaces
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# TODO; Make it optional, define it in a block
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# Note: Use "role=device" to make humpback a SPI slave
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# The ~CS pin is a global pin, but not being configured global.
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SPIResource(0,
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cs="R2", clk="C8", mosi="N5", miso="T2",
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attrs=Attrs(IO_STANDARD="SB_LVCMOS")
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),
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# Define I2C interface
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# TODO: Make it optional, declare it in a block itself
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# Use "role=device" to make humpback a I2C slave
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I2CResource(0,
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sda="T16", scl="M12",
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attrs=Attrs(IO_STANDARD="SB_LVCMOS", PULLUP=1)
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),
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]
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# Using the dict approach in (o)migen
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# Note: Numbering is required in nMigen, so some probably not very meaningful strings/integers are inserted
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connectors = [
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# EEM0 Connector
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Connector("eem", 0, {
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"d0_cc_n": "H1",
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"d0_cc_p": "J3",
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"d1_n" : "B1",
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"d1_p" : "F5",
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"d2_n" : "C2",
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"d2_p" : "C1",
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"d3_n" : "D2",
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"d3_p" : "F4",
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"d4_n" : "D1",
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"d4_p" : "G5",
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"d5_n" : "E3",
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"d5_p" : "G4",
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"d6_n" : "E2",
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"d6_p" : "H5",
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"d7_n" : "F3",
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"d7_p" : "G3",
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}),
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# EEM1 Connector
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Connector("eem", 1, {
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"d0_cc_n": "L3",
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"d0_cc_p": "L6",
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"d1_n": "F1",
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"d1_p": "H6",
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"d2_n": "G2",
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"d2_p": "H4",
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"d3_n": "H2",
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"d3_p": "J4",
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"d4_n": "J1",
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"d4_p": "J2",
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"d5_n": "K3",
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"d5_p": "K1",
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"d6_n": "L1",
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"d6_p": "L4",
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"d7_n": "M1",
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"d7_p": "K4",
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}),
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# EEM2 Connector
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Connector("eem", 2, {
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"d0_cc_n": "G1",
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"d0_cc_p": "J5",
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"d1_n": "M2",
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"d1_p": "K5",
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"d2_n": "N2",
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"d2_p": "L7",
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"d3_n": "M3",
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"d3_p": "M6",
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"d4_n": "N3",
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"d4_p": "L5",
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"d5_n": "M4",
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"d5_p": "P1",
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"d6_n": "M5",
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"d6_p": "P2",
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"d7_n": "N4",
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"d7_p": "R1",
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}),
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# STM32 Nucleo/ Arduino Connector
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# TODO: Suspect SPI mismatch forever
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Connector("stm32", "pins", {
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"PA0": "A2",
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# "PA1": "P14", # PA1 -> PB2, but PB2 has a mapping on FPGA already
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# "PA2": "B8", # PA2 -> PF6
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"PA3": "L13",
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"PA5": "C8",
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"PA6": "T2",
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# "PA7": "N12", # PA7 -> PE9, but PE9 has a mapping on FPGA already
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# "PA8": "M9", # PA8 -> PF2
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# "PA9": "P10", # PA9 -> PF1
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# "PA10": "R10", # PA10 -> PF0
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"PA15": "B14",
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"PB0": "A1",
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# "PB1": "G12", # PB1 -> PF4
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"PB1": "M14", # PC1 -> PB1
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"PB2": "B6",
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"PB5": "N5",
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# "PB6": "A7", # PB6 -> PG6
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"PB6": "T13", # PG9 -> PB6
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"PB7": "M11", # PG10 -> PB7
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"PB8": "M12",
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"PB9": "T16",
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"PB10": "C3",
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"PB11": "F7",
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"PB12": "B13",
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"PB13": "B12",
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"PB15": "A11",
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"PC0": "L14",
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# "PC1": "M14", # PC1 -> PB1
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# "PC2": "A9", # PC2 -> PF5
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"PC2": "N16", # PC4 -> PC2
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"PC3": "M16",
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# "PC4": "N16", # PC4 -> PC2
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# "PC5": "P16", # PC5 -> PF10
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"PC6": "B10",
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"PC7": "B15",
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"PC8": "H16",
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"PC9": "J10",
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"PC10": "J16",
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"PC11": "J15",
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"PC12": "K12",
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"PD0": "T9",
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"PD1": "N9",
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"PD2": "K13",
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"PD3": "T10",
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"PD4": "A6",
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"PD5": "T11",
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"PD6": "M13",
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"PD7": "L12",
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"PD11": "E5",
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"PD12": "D5",
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"PD13": "C5",
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"PD14": "R2",
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"PE0": "D3",
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"PE2": "P15",
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"PE3": "N10",
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"PE4": "R15",
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"PE5": "T15",
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"PE6": "M8",
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"PE7": "E6",
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"PE8": "D6",
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"PE9": "F12",
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"PE10": "A5",
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"PE11": "G11",
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"PE12": "B4",
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# "PE13": "F11", # PE13 -> PG12
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# "PE14": "C4", # PE14 -> PE6, but PE6 has a mapping on FPGA already
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"PE14": "B9", # PF14 -> PE14
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"PE15": "B3",
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"PF0": "R10", # PA10 -> PF0
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"PF1": "P10", # PA9 -> PF1
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"PF2": "M9", # PA8 -> PF2
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"PF4": "G12", # PB1 -> PF4
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"PF5": "A9", # PC2 -> PF5
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"PF6": "B8", # PA2 -> PF6
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"PF7": "L9",
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"PF8": "L10",
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"PF9": "P9",
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"PF10": "P16", # PC5 -> PF10
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# "PF14": "B9", # PF14 -> PE14
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# "PF15": "B16", # PF15 -> PG14
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"PG0": "M7",
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"PG1": "P8",
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"PG2": "K14",
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"PG3": "K15",
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"PG6": "A7", # PB6 -> PG6
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# "PG9": "T13", # PG9 -> PB6
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# "PG10": "M11", # PG10 -> PB7
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"PG12": "F11", # PE13 -> PG12
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"PG14": "B16", # PF15 -> PG14
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}),
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# Beaglebone Black Connector
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Connector("bb", "pins", {
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"CLKOUT": "R9",
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"GPIO0_7": "R14",
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"GPIO1_16": "A16",
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"GPIO1_17": "R3",
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"GPIO1_29": "D11",
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"GPIO1_31": "D14",
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"GPIO2_6": "D16",
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"GPIO2_7": "C16",
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"GPIO2_8": "E16",
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"GPIO2_9": "D15",
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"GPIO2_11": "F15",
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"GPIO2_13": "F16",
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"GPIO2_22": "C11",
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"GPIO2_23": "C10",
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"GPIO2_24": "E10",
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"GPIO2_25": "D4",
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"GPIO3_19": "P4",
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"GPIO3_21": "R4",
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"GPMC_A2": "T7",
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"GPMC_A3": "T1",
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"GPMC_A14": "F9",
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"GPMC_A15": "B7",
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"GPMC_AD0": "C12",
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"GPMC_AD1": "E11",
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"GPMC_AD2": "J12",
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"GPMC_AD3": "J11",
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"GPMC_AD4": "C13",
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"GPMC_AD5": "C14",
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"GPMC_AD6": "J14",
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"GPMC_AD7": "J13",
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"GPMC_AD8": "E13",
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"GPMC_AD9": "G13",
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"GPMC_AD10": "G14",
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"GPMC_AD11": "G10",
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"GPMC_AD12": "E14",
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"GPMC_AD13": "H14",
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"GPMC_AD14": "F14",
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"GPMC_AD15": "F13",
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"GPMC_ADVN": "H12",
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"GPMC_BE0N": "G16",
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"GPMC_CLK": "H11",
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"GPMC_CSN1": "D13",
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"GPMC_OEN": "H13",
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"GPMC_WE1N": "G15",
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}),
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# ESP32 Connector
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Connector("esp32", "pins", {
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"IO2": "D9",
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"IO4": "D7",
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"IO22": "C7",
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"IO34": "E9",
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"IO35": "C9",
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}),
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# OrangePI Zero Connector
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Connector("orange_pi", "pins", {
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"PG06": "A15",
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}),
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]
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eem_to_urukul = [
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Resource("eem", 1,
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Subsignal("sclk", DiffPairs("L6", "L3", dir="o", conn=("eem", 1))),
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Subsignal("mosi", DiffPairs("H6", "F1", dir="o", conn=("eem", 1))),
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Subsignal("miso", DiffPairs("H4", "G2", dir="i", conn=("eem", 1)),
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Attrs(IO_STANDARD="SB_LVDS_INPUT")),
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Subsignal("cs", DiffPairs("J4 J2 K1", "H2 J1 K3", dir="o", conn=("eem", 1))),
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Subsignal("io_update", DiffPairs("L4", "L1", dir="o", conn=("eem", 1))),
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Subsignal("sync_out", DiffPairs("K4", "M1", dir="o", conn=("emm", 1))),
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Attrs(IO_STANDARD="SB_LVCMOS")
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)
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]
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# tool chain setup, using default ICE40 HX8K evaluation code
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def toolchain_program(self, products, name):
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iceprog = os.environ.get("ICEPROG", "iceprog")
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with products.extract("{}.bin".format(name)) as bitstream_filename:
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subprocess.check_call([iceprog, "-S", bitstream_filename])
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if __name__ == "__main__":
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from nmigen_boards.test.blinky import *
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platform = HumpbackPlatform()
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platform.add_resources(platform.eem_to_urukul)
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platform.build(Blinky(), do_program=False)
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