from humpback import HumpbackPlatform from migen.fhdl.module import Module from migen.fhdl.specials import Instance from migen.fhdl.bitcontainer import value_bits_sign from migen.genlib.io import * from migen.build.lattice.common import LatticeiCE40DifferentialInputImpl from migen.genlib.io import DifferentialInput class UrukulConnector(Module): def __init__(self, platform): # Request EEM I/O & SPI # eem = platform.request("eem", 0) eem0 = platform.request("eem0", 0); eem1 = platform.request("eem0", 1); # eem2 = platform.request("eem0", 2); eem2 = platform.request("eem0_n", 2); # _ignore_eem2 = platform.request("eem0_n", 2); # miso = platform.request("miso", 0); eem3 = platform.request("eem0", 3); eem4 = platform.request("eem0", 4); eem5 = platform.request("eem0", 5); spi = platform.request("spi") led = platform.request("user_led") # Assert signal length # TODO: Refactor assertion assert len(spi.sclk) == 1 assert len(spi.mosi) == 1 # assert len(spi.miso) == 1 assert len(spi.cs) == 3 # Flip positive signal as negative output, maybe only do it for FPGA outputs # self.comb += eem.n.eq(~eem.p) self.miso_n = Signal() self.sdo = Signal() self.specials += Instance("SB_IO", p_PIN_TYPE=C(0b000001, 6), p_IO_STANDARD="SB_LVDS_INPUT", io_PACKAGE_PIN=eem2, i_D_OUT_0=self.sdo, o_D_IN_0=self.miso_n ) # self.submodules += LatticeiCE40DifferentialInputImpl(eem2.p, eem2.n, spi.miso) # self.specials += DifferentialInput(eem2, None, spi.miso) # Link EEM to SPI self.comb += [ eem0.p.eq(spi.sclk), eem0.n.eq(~spi.sclk), eem1.p.eq(spi.mosi), eem1.n.eq(~spi.mosi), # spi.miso.eq(eem2.p), spi.miso.eq(~self.miso_n), eem3.p.eq(spi.cs[0]), eem3.n.eq(~spi.cs[0]), eem4.p.eq(spi.cs[1]), eem4.n.eq(~spi.cs[1]), eem5.p.eq(spi.cs[2]), eem5.n.eq(~spi.cs[2]), led.eq(1) ] # Debug purposes: Tie EEM MISO to EEM MOSI # self.comb += eem.p[2].eq(eem.p[1]) if __name__ == "__main__": platform = HumpbackPlatform() platform.build(UrukulConnector(platform))