From f92384d649577bfcd69a0257f36d157066f85aca Mon Sep 17 00:00:00 2001
From: occheung <dc@m-labs.hk>
Date: Fri, 7 Aug 2020 17:40:06 +0800
Subject: [PATCH] humpback: fixed nucleo v2 mapping

---
 nmigen/humpback.py | 53 +++++++++++++++++++++++++++++-----------------
 1 file changed, 34 insertions(+), 19 deletions(-)

diff --git a/nmigen/humpback.py b/nmigen/humpback.py
index bb4fd8b..f8d9c25 100644
--- a/nmigen/humpback.py
+++ b/nmigen/humpback.py
@@ -128,25 +128,28 @@ class HumpbackPlatform(LatticeICE40Platform):
 		}),
 
 		# STM32 Nucleo/ Arduino Connector
-		# TODO: SPI signal matching
+		# TODO: Suspect SPI mismatch
 		Connector("stm32", "pins", {
 	        "PA0": "A2",
-			"PA1": "P14",
-			"PA2": "B8",
+#			"PA1": "P14",	# PA1 -> PB2, but PB2 has a mapping on FPGA already
+#			"PA2": "B8",	# PA2 -> PF6
 	        "PA3": "L13",
 	        "PA5": "C8",
 	        "PA6": "T2",
-		    "PA7": "N12",
-		    "PA8": "M9",
-		    "PA9": "P10",
-		    "PA10": "R10",
+#		    "PA7": "N12",	# PA7 -> PE9, but PE9 has a mapping on FPGA already
+#		    "PA8": "M9",	# PA8 -> PF2
+#		    "PA9": "P10",	# PA9 -> PF1
+#		    "PA10": "R10",	# PA10 -> PF0
 		    "PA15": "B14",
 
 		    "PB0": "A1",
-		    "PB1": "G12",
+#		    "PB1": "G12",	# PB1 -> PF4
+		    "PB1": "M14",	# PC1 -> PB1
 		    "PB2": "B6",
 		    "PB5": "N5",
-		    "PB6": "A7",
+#		    "PB6": "A7",	# PB6 -> PG6
+			"PB6": "T13",	# PG9 -> PB6
+			"PB7": "M11",	# PG10 -> PB7
 		    "PB8": "M12",
 		    "PB9": "T16",
 		    "PB10": "C3",
@@ -156,11 +159,12 @@ class HumpbackPlatform(LatticeICE40Platform):
 		    "PB15": "A11",
 
 			"PC0": "L14",
-			"PC1": "M14",
-			"PC2": "A9",
+#			"PC1": "M14",	# PC1 -> PB1
+#			"PC2": "A9",	# PC2 -> PF5
+			"PC2": "N16",	# PC4 -> PC2
 			"PC3": "M16",
-			"PC4": "N16",
-			"PC5": "P16",
+#			"PC4": "N16",	# PC4 -> PC2
+#			"PC5": "P16",	# PC5 -> PF10
 			"PC6": "B10",
 			"PC7": "B15",
 			"PC8": "H16",
@@ -194,22 +198,33 @@ class HumpbackPlatform(LatticeICE40Platform):
 			"PE10": "A5",
 			"PE11": "G11",
 			"PE12": "B4",
-			"PE13": "F11",
-			"PE14": "C4",
+#			"PE13": "F11",	# PE13 -> PG12
+#			"PE14": "C4",	# PE14 -> PE6, but PE6 has a mapping on FPGA already
+			"PE14": "B9",	# PF14 -> PE14
 			"PE15": "B3",
 
+			"PF0": "R10",	# PA10 -> PF0
+			"PF1": "P10",	# PA9 -> PF1
+			"PF2": "M9",	# PA8 -> PF2
+			"PF4": "G12",	# PB1 -> PF4
+			"PF5": "A9",	# PC2 -> PF5
+			"PF6": "B8",	# PA2 -> PF6
 	        "PF7": "L9",
 			"PF8": "L10",
 			"PF9": "P9",
-			"PF14": "B9",
-			"PF15": "B16",
+			"PF10": "P16",	# PC5 -> PF10
+#			"PF14": "B9",	# PF14 -> PE14
+#			"PF15": "B16",	# PF15 -> PG14
 
 			"PG0": "M7",
 			"PG1": "P8",
 			"PG2": "K14",
 			"PG3": "K15",
-			"PG9": "T13",
-			"PG10": "M11",
+			"PG6": "A7",	# PB6 -> PG6
+#			"PG9": "T13",	# PG9 -> PB6
+#			"PG10": "M11",	# PG10 -> PB7
+			"PG12": "F11",	# PE13 -> PG12
+			"PG14": "B16",	# PF15 -> PG14
 		}),
 
 		# Beaglebone Black Connector