forked from M-Labs/humpback-dds
main: functioning
This commit is contained in:
parent
4438032772
commit
e17cc27cbb
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@ -222,9 +222,10 @@ fn main() -> ! {
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client.network_stack.update(time);
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}
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// Process MQTT messages about Urukul/Control
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let connection = client
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.poll(|_client, topic, message, _properties| {
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info!("On '{:?}', received: {:?}", topic, message);
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info!("On {:?}, received: {:?}", topic, message);
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// Why is topic a string while message is a slice?
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mqtt_mux.process_mqtt(topic, message);
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}).is_ok();
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@ -1,7 +1,7 @@
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use embedded_hal::blocking::spi::Transfer;
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use core::assert;
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use crate::Error;
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use crate::urukul::Error;
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pub struct Attenuator<SPI> {
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spi: SPI,
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@ -1,5 +1,5 @@
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use embedded_hal::blocking::spi::Transfer;
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use crate::Error;
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use crate::urukul::Error;
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use core::mem::size_of;
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// Bitmasks for CFG
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@ -1,4 +1,4 @@
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use crate::Error;
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use crate::urukul::Error;
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use crate::spi_slave::Parts;
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use embedded_hal::{
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@ -1,5 +1,5 @@
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use embedded_hal::blocking::spi::Transfer;
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use crate::Error;
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use crate::urukul::Error;
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use core::mem::size_of;
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use core::convert::TryInto;
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use heapless::Vec;
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300
src/lib.rs
300
src/lib.rs
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@ -1,300 +0,0 @@
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#![no_std]
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#![feature(str_strip)]
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extern crate embedded_hal;
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use embedded_hal::{
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blocking::spi::Transfer,
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};
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#[macro_use]
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pub mod bitmask_macro;
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pub mod spi_slave;
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pub mod cpld;
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pub mod config_register;
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use crate::config_register::ConfigRegister;
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use crate::config_register::CFGMask;
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use crate::config_register::StatusMask;
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pub mod attenuator;
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use crate::attenuator::Attenuator;
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pub mod dds;
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use crate::dds::DDS;
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// pub mod scpi;
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// pub mod translation;
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pub mod nal_tcp_client;
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pub mod flash;
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pub mod mqtt_mux;
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/*
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* Enum for structuring error
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*/
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#[derive(Debug)]
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pub enum Error<E> {
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SPI(E),
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CSError,
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GetRefMutDataError,
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AttenuatorError,
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IOUpdateError,
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DDSError,
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ConfigRegisterError,
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DDSCLKError,
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DDSRAMError,
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ParameterError,
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MqttTopicError,
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MqttCommandError,
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}
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#[derive(Debug, Clone)]
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pub enum ClockSource {
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OSC,
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SMA,
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MMCX,
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}
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/*
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* Struct for Urukul master device
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*/
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pub struct Urukul<SPI> {
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config_register: ConfigRegister<SPI>,
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attenuator: Attenuator<SPI>,
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dds: [DDS<SPI>; 4],
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f_master_clk: f64,
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}
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impl<SPI, E> Urukul<SPI>
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where
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SPI: Transfer<u8, Error = E>,
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{
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/*
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* Master constructor for the entire Urukul device
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* Supply 7 SPI channels to Urukul and 4 reference clock frequencies
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*/
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pub fn new(spi1: SPI, spi2: SPI, spi3: SPI, spi4: SPI, spi5: SPI, spi6: SPI, spi7: SPI) -> Self {
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// Construct Urukul
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Urukul {
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config_register: ConfigRegister::new(spi1),
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attenuator: Attenuator::new(spi2),
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// Create 4 DDS instances with fixed 25MHz clock
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// Counter-intuitive to assign urukul clock before having a urukul
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dds: [
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DDS::new(spi4, 25_000_000.0),
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DDS::new(spi5, 25_000_000.0),
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DDS::new(spi6, 25_000_000.0),
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DDS::new(spi7, 25_000_000.0),
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],
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// Default clock selection: OSC, fixed 100MHz speed
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f_master_clk: 100_000_000.0,
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}
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}
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/*
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* Reset method. To be invoked by initialization and manual reset.
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* Only Urukul struct provides reset method.
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* DDS reset is controlled by Urukul (RST).
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* Attenuators only have shift register reset, which does not affect its data
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* CPLD only has a "all-zero" default state.
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*/
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pub fn reset(&mut self) -> Result<(), Error<E>> {
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// Reset DDS and attenuators
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self.config_register.set_configurations(&mut [
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(CFGMask::RST, 1),
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(CFGMask::IO_RST, 1),
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(CFGMask::IO_UPDATE, 0)
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])?;
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// Set 0 to all fields on configuration register.
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self.config_register.set_configurations(&mut [
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(CFGMask::RF_SW, 0),
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(CFGMask::LED, 0),
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(CFGMask::PROFILE, 0),
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(CFGMask::IO_UPDATE, 0),
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(CFGMask::MASK_NU, 0),
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(CFGMask::CLK_SEL0, 0),
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(CFGMask::SYNC_SEL, 0),
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(CFGMask::RST, 0),
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(CFGMask::IO_RST, 0),
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(CFGMask::CLK_SEL1, 0),
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(CFGMask::DIV, 0),
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])?;
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// Init all DDS chips. Configure SDIO as input only.
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for chip_no in 0..4 {
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self.dds[chip_no].init()?;
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}
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// Clock tree reset. OSC clock source by default
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self.f_master_clk = 100_000_000.0;
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// CPLD divides clock frequency by 4 by default.
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for chip_no in 0..4 {
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self.dds[chip_no].set_ref_clk_frequency(self.f_master_clk / 4.0)?;
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}
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Ok(())
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}
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/*
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* Test method fo Urukul.
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* Return the number of test failed.
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*/
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pub fn test(&mut self) -> Result<u32, Error<E>> {
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let mut count = self.config_register.test()?;
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count += self.attenuator.test()?;
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for chip_no in 0..4 {
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count += self.dds[chip_no].test()?;
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}
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Ok(count)
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}
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}
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impl<SPI, E> Urukul<SPI>
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where
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SPI: Transfer<u8, Error = E>
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{
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fn get_channel_switch_status(&mut self, channel: u32) -> Result<bool, Error<E>> {
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if channel < 4 {
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self.config_register.get_status(StatusMask::RF_SW).map(|val| (val & (1 << channel)) != 0)
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} else {
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Err(Error::ParameterError)
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}
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}
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fn set_channel_switch(&mut self, channel: u32, status: bool) -> Result<(), Error<E>> {
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if channel < 4 {
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let prev = u32::from(self.config_register.get_status(StatusMask::RF_SW)?);
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let next = {
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if status {
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prev | (1 << channel)
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} else {
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prev & (!(1 << channel))
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}
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};
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self.config_register.set_configurations(&mut [
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(CFGMask::RF_SW, next),
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]).map(|_| ())
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} else {
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Err(Error::ParameterError)
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}
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}
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fn set_clock(&mut self, source: ClockSource, frequency: f64, division: u8) -> Result<(), Error<E>> {
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// Change clock source through configuration register
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self.set_clock_source(source)?;
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// Modify the master clock frequency
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// Prevent redundunt call to change f_ref_clk
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self.f_master_clk = frequency;
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self.set_clock_division(division)
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}
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fn set_clock_source(&mut self, source: ClockSource) -> Result<(), Error<E>> {
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// Change clock source through configuration register
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match source {
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ClockSource::OSC => self.config_register.set_configurations(&mut [
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(CFGMask::CLK_SEL0, 0),
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(CFGMask::CLK_SEL1, 0),
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]),
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ClockSource::MMCX => self.config_register.set_configurations(&mut [
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(CFGMask::CLK_SEL0, 0),
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(CFGMask::CLK_SEL1, 1),
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]),
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ClockSource::SMA => self.config_register.set_configurations(&mut [
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(CFGMask::CLK_SEL0, 1),
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]),
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}.map(|_| ())
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}
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fn set_clock_frequency(&mut self, frequency: f64) -> Result<(), Error<E>> {
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// Update master clock frequency
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self.f_master_clk = frequency;
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// Update all DDS f_ref_clk
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self.set_dds_ref_clk()
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}
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fn set_clock_division(&mut self, division: u8) -> Result<(), Error<E>> {
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match division {
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1 => self.config_register.set_configurations(&mut [
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(CFGMask::DIV, 1),
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]),
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2 => self.config_register.set_configurations(&mut [
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(CFGMask::DIV, 2),
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]),
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4 => self.config_register.set_configurations(&mut [
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(CFGMask::DIV, 3),
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]),
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_ => Err(Error::ParameterError),
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}?;
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self.set_dds_ref_clk()
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}
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fn set_dds_ref_clk(&mut self) -> Result<(), Error<E>> {
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// Calculate reference clock frequency after clock division from configuration register
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let f_ref_clk = self.f_master_clk / (self.get_master_clock_division() as f64);
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// Update all DDS chips on reference clock frequency
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for dds_channel in 0..4 {
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self.dds[dds_channel].set_ref_clk_frequency(f_ref_clk)?;
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}
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Ok(())
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}
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fn get_master_clock_division(&mut self) -> u8 {
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match self.config_register.get_configuration(CFGMask::DIV) {
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0 | 3 => 4,
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1 => 1,
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2 => 2,
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_ => panic!("Divisor out of range, when reading configuration register (CPLD)."),
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}
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}
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fn set_channel_attenuation(&mut self, channel: u8, attenuation: f32) -> Result<(), Error<E>> {
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if channel >= 4 || attenuation < 0.0 || attenuation > 31.5 {
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return Err(Error::ParameterError);
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}
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self.attenuator.set_channel_attenuation(channel, attenuation)
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}
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fn set_profile(&mut self, profile: u8) -> Result<(), Error<E>> {
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if profile >= 8 {
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return Err(Error::ParameterError);
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}
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self.config_register.set_configurations(&mut [
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(CFGMask::PROFILE, profile.into())
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]).map(|_| ())
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}
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fn set_channel_single_tone_profile(&mut self, channel: u8, profile: u8, frequency: f64, phase: f64, amplitude: f64) -> Result<(), Error<E>> {
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if channel >= 4 || profile >= 8 || frequency < 0.0 || phase >= 360.0 ||
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phase < 0.0 || amplitude < 0.0 || amplitude > 1.0 {
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return Err(Error::ParameterError);
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}
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self.dds[usize::from(channel)].set_single_tone_profile(profile, frequency, phase, amplitude)
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}
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fn set_channel_single_tone_profile_frequency(&mut self, channel: u8, profile: u8, frequency: f64)-> Result<(), Error<E>> {
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if channel >= 4 || profile >= 8 || frequency < 0.0 {
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return Err(Error::ParameterError);
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}
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self.dds[usize::from(channel)].set_single_tone_profile_frequency(profile, frequency)
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}
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fn set_channel_single_tone_profile_phase(&mut self, channel: u8, profile: u8, phase: f64)-> Result<(), Error<E>> {
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if channel >= 4 || profile >= 8 || phase >= 360.0 || phase < 0.0 {
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return Err(Error::ParameterError);
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}
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self.dds[usize::from(channel)].set_single_tone_profile_phase(profile, phase)
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}
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fn set_channel_single_tone_profile_amplitude(&mut self, channel: u8, profile: u8, amplitude: f64)-> Result<(), Error<E>> {
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if channel >= 4 || profile >= 8 || amplitude < 0.0 || amplitude > 1.0 {
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return Err(Error::ParameterError);
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}
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self.dds[usize::from(channel)].set_single_tone_profile_amplitude(profile, amplitude)
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}
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fn set_channel_sys_clk(&mut self, channel: u8, f_sys_clk: f64) -> Result<(), Error<E>> {
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self.dds[usize::from(channel)].set_sys_clk_frequency(f_sys_clk)
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}
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}
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331
src/main.rs
331
src/main.rs
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@ -1,46 +1,89 @@
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#![no_main]
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#![no_std]
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#[macro_use]
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extern crate log;
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use log::{trace, debug, info, warn};
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use stm32h7xx_hal::hal::digital::v2::{
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InputPin,
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OutputPin,
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};
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#![feature(str_strip)]
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use log::{ trace, debug, info, warn };
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use stm32h7xx_hal::hal::digital::v2::InputPin;
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use stm32h7xx_hal::gpio::Speed;
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use stm32h7xx_hal::{pac, prelude::*, spi};
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use stm32h7xx_hal::ethernet;
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use smoltcp as net;
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use minimq::{
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embedded_nal::{IpAddr, Ipv4Addr, TcpStack},
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MqttClient, QoS
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};
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use cortex_m;
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use cortex_m_rt::entry;
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use rtic::cyccnt::{Instant, U32Ext};
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use firmware;
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use firmware::{
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attenuator::Attenuator,
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config_register::{
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ConfigRegister,
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CFGMask,
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StatusMask,
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},
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dds::{
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DDS,
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DDSCFRMask,
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},
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cpld::{
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CPLD,
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}
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};
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use heapless::Vec;
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use heapless::consts;
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#[macro_use]
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pub mod bitmask_macro;
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pub mod spi_slave;
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pub mod cpld;
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use crate::cpld::CPLD;
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pub mod config_register;
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pub mod attenuator;
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pub mod dds;
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pub mod nal_tcp_client;
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use crate::nal_tcp_client::{ NetStorage, NetworkStack };
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pub mod flash;
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use crate::flash::flash_ice40_fpga;
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pub mod mqtt_mux;
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use crate::mqtt_mux::MqttMux;
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pub mod urukul;
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use crate::urukul::Urukul;
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#[path = "../examples/util/logger.rs"]
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mod logger;
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static mut NET_STORE: NetStorage = NetStorage {
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// Placeholder for the real IP address, which is initialized at runtime.
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ip_addrs: [net::wire::IpCidr::Ipv6(
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net::wire::Ipv6Cidr::SOLICITED_NODE_PREFIX,
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)],
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neighbor_cache: [None; 8],
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routes_cache: [None; 8],
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};
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#[link_section = ".sram3.eth"]
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static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new();
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macro_rules! add_socket {
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($sockets:ident, $tx_storage:ident, $rx_storage:ident) => {
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let mut $rx_storage = [0; 4096];
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let mut $tx_storage = [0; 4096];
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let tcp_socket = {
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let tx_buffer = net::socket::TcpSocketBuffer::new(&mut $tx_storage[..]);
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let rx_buffer = net::socket::TcpSocketBuffer::new(&mut $rx_storage[..]);
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net::socket::TcpSocket::new(tx_buffer, rx_buffer)
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};
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let _handle = $sockets.add(tcp_socket);
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};
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}
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#[entry]
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fn main() -> ! {
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let mut cp = cortex_m::Peripherals::take().unwrap();
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let dp = pac::Peripherals::take().unwrap();
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cp.DWT.enable_cycle_counter();
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// Enable SRAM3 for the descriptor ring.
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dp.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit());
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// Reset RCC clock
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dp.RCC.rsr.write(|w| w.rmvf().set_bit());
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cp.SCB.invalidate_icache();
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cp.SCB.enable_icache();
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let pwr = dp.PWR.constrain();
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let vos = pwr.freeze();
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|
@ -48,6 +91,7 @@ fn main() -> ! {
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let ccdr = rcc
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.use_hse(8.mhz())
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.sys_ck(400.mhz())
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.hclk(200.mhz())
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.pll1_q_ck(48.mhz())
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.pll1_r_ck(400.mhz())
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.freeze(vos, &dp.SYSCFG);
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|
@ -65,29 +109,88 @@ fn main() -> ! {
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let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD);
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let gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE);
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let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);
|
||||
let gpiog = dp.GPIOG.split(ccdr.peripheral.GPIOG);
|
||||
|
||||
// Setup CDONE for checking
|
||||
trace!("Flashing configuration bitstream to iCE40 HX8K on Humpback.");
|
||||
delay.delay_ms(1000_u16);
|
||||
|
||||
// Using SPI_1 alternate functions (af5)
|
||||
let fpga_sck = gpiob.pb3.into_alternate_af5();
|
||||
let fpga_sdo = gpiob.pb4.into_alternate_af5();
|
||||
let fpga_sdi = gpiob.pb5.into_alternate_af5();
|
||||
|
||||
// Setup SPI_SS_B and CRESET_B
|
||||
let fpga_ss = gpioa.pa4.into_push_pull_output();
|
||||
let fpga_creset = gpiof.pf3.into_open_drain_output();
|
||||
|
||||
// Setup CDONE
|
||||
let fpga_cdone = gpiod.pd15.into_pull_up_input();
|
||||
|
||||
match fpga_cdone.is_high() {
|
||||
Ok(true) => info!("FPGA is ready."),
|
||||
Ok(_) => info!("FPGA is in reset state."),
|
||||
Err(_) => info!("Error: Cannot read C_DONE"),
|
||||
// Setup SPI interface
|
||||
let fpga_cfg_spi = dp.SPI1.spi(
|
||||
(fpga_sck, fpga_sdo, fpga_sdi),
|
||||
spi::MODE_3,
|
||||
12.mhz(),
|
||||
ccdr.peripheral.SPI1,
|
||||
&ccdr.clocks,
|
||||
);
|
||||
|
||||
flash_ice40_fpga(fpga_cfg_spi, fpga_ss, fpga_creset, fpga_cdone, delay).unwrap();
|
||||
|
||||
// Configure ethernet IO
|
||||
{
|
||||
let _rmii_refclk = gpioa.pa1.into_alternate_af11().set_speed(Speed::VeryHigh);
|
||||
let _rmii_mdio = gpioa.pa2.into_alternate_af11().set_speed(Speed::VeryHigh);
|
||||
let _rmii_mdc = gpioc.pc1.into_alternate_af11().set_speed(Speed::VeryHigh);
|
||||
let _rmii_crs_dv = gpioa.pa7.into_alternate_af11().set_speed(Speed::VeryHigh);
|
||||
let _rmii_rxd0 = gpioc.pc4.into_alternate_af11().set_speed(Speed::VeryHigh);
|
||||
let _rmii_rxd1 = gpioc.pc5.into_alternate_af11().set_speed(Speed::VeryHigh);
|
||||
let _rmii_tx_en = gpiog.pg11.into_alternate_af11().set_speed(Speed::VeryHigh);
|
||||
let _rmii_txd0 = gpiog.pg13.into_alternate_af11().set_speed(Speed::VeryHigh);
|
||||
let _rmii_txd1 = gpiob.pb13.into_alternate_af11().set_speed(Speed::VeryHigh);
|
||||
}
|
||||
|
||||
// Configure ethernet
|
||||
let mac_addr = net::wire::EthernetAddress([0xAC, 0x6F, 0x7A, 0xDE, 0xD6, 0xC8]);
|
||||
let (eth_dma, mut eth_mac) = unsafe {
|
||||
ethernet::new_unchecked(
|
||||
dp.ETHERNET_MAC,
|
||||
dp.ETHERNET_MTL,
|
||||
dp.ETHERNET_DMA,
|
||||
&mut DES_RING,
|
||||
mac_addr.clone(),
|
||||
)
|
||||
};
|
||||
|
||||
unsafe { ethernet::enable_interrupt() }
|
||||
|
||||
let store = unsafe { &mut NET_STORE };
|
||||
|
||||
store.ip_addrs[0] = net::wire::IpCidr::new(net::wire::IpAddress::v4(192, 168, 1, 200), 24);
|
||||
|
||||
let neighbor_cache = net::iface::NeighborCache::new(&mut store.neighbor_cache[..]);
|
||||
|
||||
let mut routes = net::iface::Routes::new(&mut store.routes_cache[..]);
|
||||
let default_v4_gw = net::wire::Ipv4Address::new(192, 168, 1, 1);
|
||||
routes.add_default_ipv4_route(default_v4_gw).unwrap();
|
||||
|
||||
let mut net_interface = net::iface::EthernetInterfaceBuilder::new(eth_dma)
|
||||
.ethernet_addr(mac_addr)
|
||||
.neighbor_cache(neighbor_cache)
|
||||
.ip_addrs(&mut store.ip_addrs[..])
|
||||
.routes(routes)
|
||||
.finalize();
|
||||
|
||||
/*
|
||||
* Using SPI1, AF5
|
||||
* SCLK -> PA5
|
||||
* MOSI -> PB5
|
||||
* MISO -> PA6
|
||||
* Using SPI6
|
||||
* SCLK -> PA5 (af8)
|
||||
* MOSI -> PG14 (af5)
|
||||
* MISO -> PA6 (af8)
|
||||
* CS -> 0: PB12, 1: PA15, 2: PC7
|
||||
*/
|
||||
|
||||
let sclk = gpioa.pa5.into_alternate_af5();
|
||||
let mosi = gpiob.pb5.into_alternate_af5();
|
||||
let miso = gpioa.pa6.into_alternate_af5();
|
||||
|
||||
|
||||
let sclk = gpioa.pa5.into_alternate_af8().set_speed(Speed::VeryHigh);
|
||||
let mosi = gpiog.pg14.into_alternate_af5().set_speed(Speed::VeryHigh);
|
||||
let miso = gpioa.pa6.into_alternate_af8().set_speed(Speed::VeryHigh);
|
||||
let (cs0, cs1, cs2) = (
|
||||
gpiob.pb12.into_push_pull_output(),
|
||||
gpioa.pa15.into_push_pull_output(),
|
||||
|
@ -99,112 +202,86 @@ fn main() -> ! {
|
|||
*/
|
||||
let io_update = gpiob.pb15.into_push_pull_output();
|
||||
|
||||
let spi = dp.SPI1.spi(
|
||||
let spi = dp.SPI6.spi(
|
||||
(sclk, miso, mosi),
|
||||
spi::MODE_0,
|
||||
3.mhz(),
|
||||
ccdr.peripheral.SPI1,
|
||||
2.mhz(),
|
||||
ccdr.peripheral.SPI6,
|
||||
&ccdr.clocks,
|
||||
);
|
||||
|
||||
let switch = CPLD::new(spi, (cs0, cs1, cs2), io_update);
|
||||
let parts = switch.split();
|
||||
|
||||
let mut config = ConfigRegister::new(parts.spi1);
|
||||
let mut att = Attenuator::new(parts.spi2);
|
||||
let mut dds0 = DDS::new(parts.spi4, 25_000_000.0);
|
||||
let mut urukul = Urukul::new(
|
||||
parts.spi1, parts.spi2, parts.spi3, parts.spi4, parts.spi5, parts.spi6, parts.spi7
|
||||
);
|
||||
|
||||
// Reset all DDS, set CLK_SEL to 0
|
||||
config.set_configurations(&mut [
|
||||
(CFGMask::RST, 1),
|
||||
(CFGMask::IO_RST, 1),
|
||||
(CFGMask::IO_UPDATE, 0)
|
||||
]).unwrap();
|
||||
urukul.reset().unwrap();
|
||||
info!("Test value: {}", urukul.test().unwrap());
|
||||
|
||||
config.set_configurations(&mut [
|
||||
(CFGMask::IO_RST, 0),
|
||||
(CFGMask::RST, 0),
|
||||
(CFGMask::RF_SW, 13),
|
||||
(CFGMask::DIV, 3)
|
||||
]).unwrap();
|
||||
let mut mqtt_mux = MqttMux::new(urukul);
|
||||
|
||||
dds0.init().unwrap();
|
||||
// Time unit in ms
|
||||
let mut time: u32 = 0;
|
||||
|
||||
dds0.set_configurations(&mut [
|
||||
(DDSCFRMask::PDCLK_ENABLE, 0),
|
||||
(DDSCFRMask::READ_EFFECTIVE_FTW, 1),
|
||||
]).unwrap();
|
||||
// Cycle counter for 1 ms
|
||||
// This effectively provides a conversion from rtic unit to ms
|
||||
let mut next_ms = Instant::now();
|
||||
next_ms += 400_000.cycles();
|
||||
|
||||
dds0.set_sys_clk_frequency(1_000_000_000.0).unwrap();
|
||||
let mut socket_set_entries: [_; 8] = Default::default();
|
||||
let mut sockets = net::socket::SocketSet::new(&mut socket_set_entries[..]);
|
||||
add_socket!(sockets, rx_storage, tx_storage);
|
||||
|
||||
// Attenuator
|
||||
att.set_attenuation([
|
||||
5.0, 31.5, 24.0, 0.0
|
||||
]).unwrap();
|
||||
let tcp_stack = NetworkStack::new(&mut net_interface, sockets);
|
||||
|
||||
dds0.set_single_tone_profile(1, 10_000_000.0, 0.0, 0.5).unwrap();
|
||||
config.set_configurations(&mut [
|
||||
(CFGMask::PROFILE, 1),
|
||||
]).unwrap();
|
||||
// Case dealt: Ethernet connection break down, neither side has timeout
|
||||
// Limitation: Timeout inequality will cause TCP socket state to desync
|
||||
// Probably fixed in latest smoltcp commit
|
||||
let mut client = MqttClient::<consts::U256, _>::new(
|
||||
IpAddr::V4(Ipv4Addr::new(192, 168, 1, 125)),
|
||||
"Nucleo",
|
||||
tcp_stack,
|
||||
)
|
||||
.unwrap();
|
||||
|
||||
// // Setup RAM configuration
|
||||
// dds0.set_configurations(&mut [
|
||||
// (DDSCFRMask::RAM_ENABLE, 1),
|
||||
// (DDSCFRMask::RAM_PLAYBACK_DST, 2),
|
||||
// ]).unwrap();
|
||||
let mut tick = false;
|
||||
let mut has_subscribed = false;
|
||||
|
||||
// // Configure RAM profile 0
|
||||
// dds0.write_register(0x0E, &mut [
|
||||
// 0x00, // Open
|
||||
// 0x09, 0xC4, // Address step rate (2500)
|
||||
// 0xFF, 0xC0, // End at address 1023
|
||||
// 0x00, 0x00, // Start at address 0
|
||||
// 0x04, // Recirculate mode
|
||||
// ]).unwrap();
|
||||
loop {
|
||||
// Update time accumulator in ms
|
||||
// Tick once every ms
|
||||
if Instant::now() > next_ms {
|
||||
tick = true;
|
||||
time += 1;
|
||||
next_ms += 400_000.cycles();
|
||||
}
|
||||
|
||||
// debug!("{:#X?}", dds0.read_register(0x0E, &mut[
|
||||
// 0x00, 0x00, 0x00, 0x00,
|
||||
// 0x00, 0x00, 0x00, 0x00,
|
||||
// ]).unwrap());
|
||||
// eth Poll if necessary
|
||||
// Do not poll if eth link is down
|
||||
if tick && client.network_stack.update_delay(time) == 0 && eth_mac.phy_poll_link() {
|
||||
client.network_stack.update(time);
|
||||
}
|
||||
|
||||
// // Choose profile 0
|
||||
// config.set_configurations(&mut [
|
||||
// (CFGMask::PROFILE, 0),
|
||||
// ]).unwrap();
|
||||
// Process MQTT messages about Urukul/Control
|
||||
let connection = client
|
||||
.poll(|_client, topic, message, _properties| {
|
||||
info!("On {:?}, received: {:?}", topic, message);
|
||||
// Why is topic a string while message is a slice?
|
||||
mqtt_mux.process_mqtt(topic, message);
|
||||
}).is_ok();
|
||||
|
||||
// // Set RAM to be amplitudes, disable RAM momentarily
|
||||
// dds0.set_configurations(&mut [
|
||||
// (DDSCFRMask::RAM_PLAYBACK_DST, 0),
|
||||
// (DDSCFRMask::RAM_ENABLE, 0),
|
||||
// ]).unwrap();
|
||||
if connection && !has_subscribed && tick {
|
||||
match client.subscribe("Urukul/Control/#", &[]) {
|
||||
Ok(()) => has_subscribed = true,
|
||||
Err(minimq::Error::NotReady) => {},
|
||||
e => warn!("{:?}", e),
|
||||
};
|
||||
}
|
||||
|
||||
// let mut ram_data: [u8; ((1024 * 4) + 1)] = [0; (1024 * 4) + 1];
|
||||
// ram_data[0] = 0x16;
|
||||
// for index in 0..1024 {
|
||||
// if index % 2 == 1 {
|
||||
// ram_data[(index * 4) + 1] = 0x3F;
|
||||
// ram_data[(index * 4) + 2] = 0xFF;
|
||||
// } else {
|
||||
// ram_data[(index * 4) + 1] = 0x00;
|
||||
// ram_data[(index * 4) + 2] = 0x00;
|
||||
// }
|
||||
// // ram_data[(index * 4) + 1] = ((index >> 2) & 0xFF) as u8;
|
||||
// // ram_data[(index * 4) + 2] = ((index & 0x03) << 6) as u8;
|
||||
// }
|
||||
// dds0.transfer(&mut ram_data).unwrap();
|
||||
|
||||
// config.set_configurations(&mut [
|
||||
// (CFGMask::PROFILE, 1),
|
||||
// ]).unwrap();
|
||||
|
||||
// config.set_configurations(&mut [
|
||||
// (CFGMask::PROFILE, 0),
|
||||
// ]).unwrap();
|
||||
|
||||
// dds0.set_configurations(&mut [
|
||||
// (DDSCFRMask::RAM_ENABLE, 1),
|
||||
// ]).unwrap();
|
||||
|
||||
loop {}
|
||||
// Reset tick flag
|
||||
tick = false;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -10,9 +10,9 @@ use nom::number::complete::{float, double};
|
|||
|
||||
use embedded_hal::blocking::spi::Transfer;
|
||||
use core::convert::TryInto;
|
||||
use crate::ClockSource as UrukulClockSource;
|
||||
use crate::Urukul;
|
||||
use crate::Error;
|
||||
use crate::urukul::ClockSource as UrukulClockSource;
|
||||
use crate::urukul::Urukul;
|
||||
use crate::urukul::Error;
|
||||
|
||||
#[derive(Debug, Clone)]
|
||||
pub enum MqttTopic {
|
||||
|
|
|
@ -3,7 +3,7 @@ use embedded_hal::{
|
|||
digital::v2::OutputPin,
|
||||
};
|
||||
use crate::cpld::CPLD;
|
||||
use crate::Error;
|
||||
use crate::urukul::Error;
|
||||
|
||||
pub struct SPISlave<'a, SPI, CS0, CS1, CS2, GPIO> (
|
||||
// SPI device to be multiplexed
|
||||
|
|
Loading…
Reference in New Issue