forked from M-Labs/humpback-dds
urukul: add commented code, but with lifetime conflict
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70
src/lib.rs
70
src/lib.rs
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@ -16,13 +16,14 @@ use cortex_m_semihosting::hprintln;
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pub mod bitmask_macro;
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pub mod bitmask_macro;
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pub mod spi_slave;
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pub mod spi_slave;
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// use crate::spi_slave::{
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use crate::spi_slave::{
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// Parts,
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Parts,
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// SPISlave,
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SPISlave,
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// };
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};
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pub mod cpld;
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pub mod cpld;
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use crate::cpld::CPLD;
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use crate::cpld::CPLD;
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use crate::cpld::DoOnGetRefMutData;
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pub mod config_register;
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pub mod config_register;
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use crate::config_register::ConfigRegister;
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use crate::config_register::ConfigRegister;
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@ -63,12 +64,9 @@ where
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{
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{
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/*
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/*
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* Master constructor for the entire Urukul device
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* Master constructor for the entire Urukul device
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* Supply 7 SPI channels to Urukul and 4 reference clock frequencies
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*/
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*/
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pub fn new(spi1: SPI, spi2: SPI, spi3: SPI, spi4: SPI, spi5: SPI, spi6: SPI, spi7: SPI, f_ref_clks: [u64; 4]) -> Self {
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pub fn new(spi1: SPI, spi2: SPI, spi3: SPI, spi4: SPI, spi5: SPI, spi6: SPI, spi7: SPI, f_ref_clks: [u64; 4]) -> Self {
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// Construct cpld and get parts
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// let switch = CPLD::new(spi, chip_select, io_update);
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// let parts = switch.split();
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// Construct Urukul
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// Construct Urukul
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Urukul {
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Urukul {
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config_register: ConfigRegister::new(spi1),
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config_register: ConfigRegister::new(spi1),
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@ -79,7 +77,59 @@ where
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DDS::new(spi6, f_ref_clks[2]),
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DDS::new(spi6, f_ref_clks[2]),
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DDS::new(spi7, f_ref_clks[3]),
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DDS::new(spi7, f_ref_clks[3]),
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],
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],
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// _phantom: PhantomData,
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}
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}
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}
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}
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}
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}
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// /*
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// * Struct for a better Urukul master device
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// */
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// pub struct BetterUrukul<'a, SPI, CS0, CS1, CS2, GPIO> {
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// cpld: CPLD<SPI, CS0, CS1, CS2, GPIO>,
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// parts: Option<Parts<'a, CPLD<SPI, CS0, CS1, CS2, GPIO>, SPI, CS0, CS1, CS2, GPIO>>,
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// config_register: Option<ConfigRegister<SPISlave<'a, CPLD<SPI, CS0, CS1, CS2, GPIO>, SPI, CS0, CS1, CS2, GPIO>>>,
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// attenuator: Option<Attenuator<SPISlave<'a, CPLD<SPI, CS0, CS1, CS2, GPIO>, SPI, CS0, CS1, CS2, GPIO>>>,
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// dds: [Option<DDS<SPISlave<'a, CPLD<SPI, CS0, CS1, CS2, GPIO>, SPI, CS0, CS1, CS2, GPIO>>>; 4],
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// }
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// impl<'a, SPI, CS0, CS1, CS2, GPIO> BetterUrukul<'a, SPI, CS0, CS1, CS2, GPIO>
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// where
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// SPI: Transfer<u8>,
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// CS0: OutputPin,
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// CS1: OutputPin,
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// CS2: OutputPin,
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// GPIO: OutputPin,
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// {
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// pub fn new(spi: SPI, chip_select: (CS0, CS1, CS2), io_update: GPIO) -> Self {
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// // let switch = CPLD::new(spi, chip_select, io_update);
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// // let parts = switch.split();
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// // Construct Urukul
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// BetterUrukul {
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// cpld: CPLD::new(spi, chip_select, io_update),
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// // parts: CPLD::new(spi, chip_select, io_update).split(),
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// // config_register: ConfigRegister::new(self.parts.spi1),
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// // attenuator: Attenuator::new(self.parts.spi2),
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// // dds: [
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// // DDS::new(self.parts.spi4, f_ref_clks[1]),
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// // DDS::new(self.parts.spi5, f_ref_clks[1]),
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// // DDS::new(self.parts.spi6, f_ref_clks[2]),
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// // DDS::new(self.parts.spi7, f_ref_clks[3]),
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// // ],
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// parts: None,
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// config_register: None,
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// attenuator: None,
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// dds: [None, None, None, None],
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// }
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// }
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// pub fn init(&'a mut self, f_ref_clks:[u64; 4]) {
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// self.parts = Some(self.cpld.split());
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// self.config_register = Some(ConfigRegister::new(self.parts.unwrap().spi1));
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// self.attenuator = Some(Attenuator::new(self.parts.unwrap().spi2));
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// self.dds[0] = Some(DDS::new(self.parts.unwrap().spi4, f_ref_clks[0]));
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// self.dds[1] = Some(DDS::new(self.parts.unwrap().spi5, f_ref_clks[1]));
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// self.dds[2] = Some(DDS::new(self.parts.unwrap().spi6, f_ref_clks[2]));
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// self.dds[3] = Some(DDS::new(self.parts.unwrap().spi7, f_ref_clks[3]));
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// }
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// }
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